mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 14:10:43 +00:00
2cf78f951b
Define bootscript address in RAM via DT property and remove it from config file. Adding default value to common DTSI. Platform DT description can remove this property or rewrite it. In Zynq case scriptaddr property was defined twice for no reason. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/d36ffeb00ed8f0ca4bb67d4983d1852d01ade637.1691067102.git.michal.simek@amd.com
578 lines
13 KiB
Text
578 lines
13 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Xilinx Zynq 7000 DTSI
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* Describes the hardware common to all Zynq 7000-based boards.
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*
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* Copyright (C) 2011 - 2015 Xilinx
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,zynq-7000";
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options {
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u-boot {
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compatible = "u-boot,config";
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bootscr-address = /bits/ 64 <0x3000000>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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clocks = <&clkc 3>;
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clock-latency = <1000>;
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cpu0-supply = <®ulator_vccpint>;
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operating-points = <
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/* kHz uV */
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666667 1000000
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333334 1000000
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>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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clocks = <&clkc 3>;
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};
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};
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fpga_full: fpga-full {
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compatible = "fpga-region";
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fpga-mgr = <&devcfg>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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};
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pmu@f8891000 {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 5 4>, <0 6 4>;
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interrupt-parent = <&intc>;
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reg = <0xf8891000 0x1000>,
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<0xf8893000 0x1000>;
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};
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regulator_vccpint: fixedregulator {
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compatible = "regulator-fixed";
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regulator-name = "VCCPINT";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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replicator {
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compatible = "arm,coresight-static-replicator";
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clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
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clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
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out-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* replicator output ports */
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port@0 {
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reg = <0>;
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replicator_out_port0: endpoint {
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remote-endpoint = <&tpiu_in_port>;
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};
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};
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port@1 {
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reg = <1>;
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replicator_out_port1: endpoint {
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remote-endpoint = <&etb_in_port>;
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};
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};
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};
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in-ports {
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/* replicator input port */
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port {
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replicator_in_port0: endpoint {
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remote-endpoint = <&funnel_out_port>;
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};
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};
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};
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};
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amba: axi {
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bootph-all;
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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adc: adc@f8007100 {
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compatible = "xlnx,zynq-xadc-1.00.a";
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reg = <0xf8007100 0x20>;
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interrupts = <0 7 4>;
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interrupt-parent = <&intc>;
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clocks = <&clkc 12>;
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};
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can0: can@e0008000 {
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compatible = "xlnx,zynq-can-1.0";
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status = "disabled";
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clocks = <&clkc 19>, <&clkc 36>;
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clock-names = "can_clk", "pclk";
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reg = <0xe0008000 0x1000>;
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interrupts = <0 28 4>;
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interrupt-parent = <&intc>;
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tx-fifo-depth = <0x40>;
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rx-fifo-depth = <0x40>;
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};
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can1: can@e0009000 {
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compatible = "xlnx,zynq-can-1.0";
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status = "disabled";
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clocks = <&clkc 20>, <&clkc 37>;
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clock-names = "can_clk", "pclk";
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reg = <0xe0009000 0x1000>;
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interrupts = <0 51 4>;
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interrupt-parent = <&intc>;
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tx-fifo-depth = <0x40>;
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rx-fifo-depth = <0x40>;
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};
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gpio0: gpio@e000a000 {
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compatible = "xlnx,zynq-gpio-1.0";
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#gpio-cells = <2>;
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clocks = <&clkc 42>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <0 20 4>;
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reg = <0xe000a000 0x1000>;
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};
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i2c0: i2c@e0004000 {
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compatible = "cdns,i2c-r1p10";
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status = "disabled";
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clocks = <&clkc 38>;
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interrupt-parent = <&intc>;
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interrupts = <0 25 4>;
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clock-frequency = <400000>;
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reg = <0xe0004000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c1: i2c@e0005000 {
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compatible = "cdns,i2c-r1p10";
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status = "disabled";
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clocks = <&clkc 39>;
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interrupt-parent = <&intc>;
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interrupts = <0 48 4>;
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clock-frequency = <400000>;
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reg = <0xe0005000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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intc: interrupt-controller@f8f01000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xF8F01000 0x1000>,
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<0xF8F00100 0x100>;
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};
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L2: cache-controller@f8f02000 {
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compatible = "arm,pl310-cache";
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reg = <0xF8F02000 0x1000>;
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interrupts = <0 2 4>;
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arm,data-latency = <3 2 2>;
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arm,tag-latency = <2 2 2>;
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cache-unified;
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cache-level = <2>;
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};
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mc: memory-controller@f8006000 {
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compatible = "xlnx,zynq-ddrc-a05";
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reg = <0xf8006000 0x1000>;
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};
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ocm: sram@fffc0000 {
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compatible = "mmio-sram";
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reg = <0xfffc0000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xfffc0000 0x10000>;
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ocm-sram@0 {
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reg = <0x0 0x10000>;
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};
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};
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uart0: serial@e0000000 {
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compatible = "xlnx,xuartps", "cdns,uart-r1p8";
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status = "disabled";
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clocks = <&clkc 23>, <&clkc 40>;
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clock-names = "uart_clk", "pclk";
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reg = <0xE0000000 0x1000>;
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interrupts = <0 27 4>;
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};
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uart1: serial@e0001000 {
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compatible = "xlnx,xuartps", "cdns,uart-r1p8";
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status = "disabled";
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clocks = <&clkc 24>, <&clkc 41>;
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clock-names = "uart_clk", "pclk";
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reg = <0xE0001000 0x1000>;
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interrupts = <0 50 4>;
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};
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spi0: spi@e0006000 {
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compatible = "xlnx,zynq-spi-r1p6";
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reg = <0xe0006000 0x1000>;
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status = "disabled";
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interrupt-parent = <&intc>;
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interrupts = <0 26 4>;
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clocks = <&clkc 25>, <&clkc 34>;
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clock-names = "ref_clk", "pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@e0007000 {
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compatible = "xlnx,zynq-spi-r1p6";
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reg = <0xe0007000 0x1000>;
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status = "disabled";
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interrupt-parent = <&intc>;
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interrupts = <0 49 4>;
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clocks = <&clkc 26>, <&clkc 35>;
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clock-names = "ref_clk", "pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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qspi: spi@e000d000 {
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compatible = "xlnx,zynq-qspi-1.0";
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reg = <0xe000d000 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <0 19 4>;
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clocks = <&clkc 10>, <&clkc 43>;
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clock-names = "ref_clk", "pclk";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gem0: ethernet@e000b000 {
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compatible = "xlnx,zynq-gem", "cdns,gem";
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reg = <0xe000b000 0x1000>;
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status = "disabled";
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interrupts = <0 22 4>;
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clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
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clock-names = "pclk", "hclk", "tx_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gem1: ethernet@e000c000 {
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compatible = "xlnx,zynq-gem", "cdns,gem";
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reg = <0xe000c000 0x1000>;
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status = "disabled";
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interrupts = <0 45 4>;
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clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
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clock-names = "pclk", "hclk", "tx_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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smcc: memory-controller@e000e000 {
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compatible = "arm,pl353-smc-r2p1", "arm,primecell";
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reg = <0xe000e000 0x0001000>;
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status = "disabled";
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clock-names = "memclk", "apb_pclk";
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clocks = <&clkc 11>, <&clkc 44>;
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ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
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0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
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0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
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#address-cells = <2>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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interrupts = <0 18 4>;
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nfc0: nand-controller@0,0 {
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compatible = "arm,pl353-nand-r2p1";
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reg = <0 0 0x1000000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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nor0: flash@1,0 {
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status = "disabled";
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compatible = "cfi-flash";
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reg = <1 0 0x2000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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sdhci0: mmc@e0100000 {
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compatible = "arasan,sdhci-8.9a";
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status = "disabled";
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&clkc 21>, <&clkc 32>;
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interrupt-parent = <&intc>;
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interrupts = <0 24 4>;
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reg = <0xe0100000 0x1000>;
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};
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sdhci1: mmc@e0101000 {
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compatible = "arasan,sdhci-8.9a";
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status = "disabled";
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&clkc 22>, <&clkc 33>;
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interrupt-parent = <&intc>;
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interrupts = <0 47 4>;
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reg = <0xe0101000 0x1000>;
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};
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slcr: slcr@f8000000 {
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bootph-all;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
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reg = <0xF8000000 0x1000>;
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ranges;
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clkc: clkc@100 {
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bootph-all;
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#clock-cells = <1>;
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compatible = "xlnx,ps7-clkc";
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fclk-enable = <0xf>;
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clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
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"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
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"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
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"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
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"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
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"dma", "usb0_aper", "usb1_aper", "gem0_aper",
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"gem1_aper", "sdio0_aper", "sdio1_aper",
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"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
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"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
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"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
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"dbg_trc", "dbg_apb";
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reg = <0x100 0x100>;
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};
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rstc: rstc@200 {
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compatible = "xlnx,zynq-reset";
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reg = <0x200 0x48>;
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#reset-cells = <1>;
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syscon = <&slcr>;
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};
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pinctrl0: pinctrl@700 {
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compatible = "xlnx,pinctrl-zynq";
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reg = <0x700 0x200>;
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syscon = <&slcr>;
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};
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};
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dmac_s: dma-controller@f8003000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xf8003000 0x1000>;
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interrupt-parent = <&intc>;
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/*
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* interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
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* "dma4", "dma5", "dma6", "dma7";
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*/
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interrupts = <0 13 4>,
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<0 14 4>, <0 15 4>,
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<0 16 4>, <0 17 4>,
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<0 40 4>, <0 41 4>,
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<0 42 4>, <0 43 4>;
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#dma-cells = <1>;
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clocks = <&clkc 27>;
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clock-names = "apb_pclk";
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};
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devcfg: devcfg@f8007000 {
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compatible = "xlnx,zynq-devcfg-1.0";
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reg = <0xf8007000 0x100>;
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interrupt-parent = <&intc>;
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interrupts = <0 8 4>;
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clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
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clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
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syscon = <&slcr>;
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};
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efuse: efuse@f800d000 {
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compatible = "xlnx,zynq-efuse";
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reg = <0xf800d000 0x20>;
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};
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global_timer: timer@f8f00200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0xf8f00200 0x20>;
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interrupts = <1 11 0x301>;
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interrupt-parent = <&intc>;
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clocks = <&clkc 4>;
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};
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ttc0: timer@f8001000 {
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interrupt-parent = <&intc>;
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interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
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compatible = "cdns,ttc";
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clocks = <&clkc 6>;
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reg = <0xF8001000 0x1000>;
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};
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ttc1: timer@f8002000 {
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interrupt-parent = <&intc>;
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interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
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compatible = "cdns,ttc";
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clocks = <&clkc 6>;
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reg = <0xF8002000 0x1000>;
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};
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scutimer: timer@f8f00600 {
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bootph-all;
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interrupt-parent = <&intc>;
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interrupts = <1 13 0x301>;
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xf8f00600 0x20>;
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clocks = <&clkc 4>;
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};
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usb0: usb@e0002000 {
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compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
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status = "disabled";
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clocks = <&clkc 28>;
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interrupt-parent = <&intc>;
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interrupts = <0 21 4>;
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reg = <0xe0002000 0x1000>;
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phy_type = "ulpi";
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};
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usb1: usb@e0003000 {
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compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
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status = "disabled";
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clocks = <&clkc 29>;
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interrupt-parent = <&intc>;
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interrupts = <0 44 4>;
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reg = <0xe0003000 0x1000>;
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phy_type = "ulpi";
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};
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watchdog0: watchdog@f8005000 {
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clocks = <&clkc 45>;
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compatible = "cdns,wdt-r1p2";
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interrupt-parent = <&intc>;
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interrupts = <0 9 1>;
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reg = <0xf8005000 0x1000>;
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timeout-sec = <10>;
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};
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etb@f8801000 {
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0xf8801000 0x1000>;
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clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
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clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
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in-ports {
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port {
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etb_in_port: endpoint {
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remote-endpoint = <&replicator_out_port1>;
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};
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};
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};
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};
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|
|
|
tpiu@f8803000 {
|
|
compatible = "arm,coresight-tpiu", "arm,primecell";
|
|
reg = <0xf8803000 0x1000>;
|
|
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
|
|
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
|
|
in-ports {
|
|
port {
|
|
tpiu_in_port: endpoint {
|
|
remote-endpoint = <&replicator_out_port0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@f8804000 {
|
|
compatible = "arm,coresight-static-funnel", "arm,primecell";
|
|
reg = <0xf8804000 0x1000>;
|
|
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
|
|
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
|
|
|
|
/* funnel output ports */
|
|
out-ports {
|
|
port {
|
|
funnel_out_port: endpoint {
|
|
remote-endpoint =
|
|
<&replicator_in_port0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
/* funnel input ports */
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel0_in_port0: endpoint {
|
|
remote-endpoint = <&ptm0_out_port>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
funnel0_in_port1: endpoint {
|
|
remote-endpoint = <&ptm1_out_port>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
funnel0_in_port2: endpoint {
|
|
};
|
|
};
|
|
/* The other input ports are not connect to anything */
|
|
};
|
|
};
|
|
|
|
ptm@f889c000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0xf889c000 0x1000>;
|
|
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
|
|
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
|
|
cpu = <&cpu0>;
|
|
out-ports {
|
|
port {
|
|
ptm0_out_port: endpoint {
|
|
remote-endpoint = <&funnel0_in_port0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ptm@f889d000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0xf889d000 0x1000>;
|
|
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
|
|
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
|
|
cpu = <&cpu1>;
|
|
out-ports {
|
|
port {
|
|
ptm1_out_port: endpoint {
|
|
remote-endpoint = <&funnel0_in_port1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|