mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 14:10:43 +00:00
13e364b3d2
The node has become useless, as described in the
commit 754815b854 ("video: stm32: remove the compatible "synopsys, dw-mipi-dsi" support")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
235 lines
5.9 KiB
Text
235 lines
5.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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#include <stm32f7-u-boot.dtsi>
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/{
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chosen {
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bootargs = "root=/dev/ram rdinit=/linuxrc";
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};
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aliases {
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/* Aliases for gpios so as to use sequence */
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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gpio9 = &gpioj;
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gpio10 = &gpiok;
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mmc0 = &sdio2;
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spi0 = &qspi;
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};
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button1 {
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compatible = "st,button1";
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button-gpio = <&gpioa 0 0>;
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};
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led1 {
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compatible = "st,led1";
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led-gpio = <&gpioj 5 0>;
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};
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panel: panel {
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compatible = "orisetech,otm8009a";
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reset-gpios = <&gpioj 15 1>;
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status = "okay";
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port {
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panel_in: endpoint {
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remote-endpoint = <&dsi_out>;
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};
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};
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};
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soc {
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dsi: dsi@40016c00 {
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compatible = "st,stm32-dsi";
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reg = <0x40016c00 0x800>;
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resets = <&rcc STM32F7_APB2_RESET(DSI)>;
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clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
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<&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
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<&clk_hse>;
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clock-names = "pclk", "px_clk", "ref";
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bootph-all;
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status = "okay";
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ports {
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port@0 {
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dsi_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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port@1 {
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dsi_in: endpoint {
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remote-endpoint = <&dp_out>;
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};
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};
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};
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};
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ltdc: display-controller@40016800 {
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compatible = "st,stm32-ltdc";
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reg = <0x40016800 0x200>;
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resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
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clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
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status = "okay";
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bootph-all;
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ports {
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port@0 {
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dp_out: endpoint {
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remote-endpoint = <&dsi_in>;
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};
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};
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};
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};
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};
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};
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&fmc {
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/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
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bank1: bank@0 {
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bootph-all;
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st,sdram-control = /bits/ 8 <NO_COL_8
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NO_ROW_12
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MWIDTH_32
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BANKS_4
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CAS_3
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SDCLK_2
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RD_BURST_EN
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RD_PIPE_DL_0>;
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st,sdram-timing = /bits/ 8 <TMRD_2
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TXSR_6
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TRAS_4
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TRC_6
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TWR_2
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TRP_2
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TRCD_2>;
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/* refcount = (64msec/total_row_sdram)*freq - 20 */
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st,sdram-refcount = < 1542 >;
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};
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};
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&pinctrl {
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ethernet_mii: mii@0 {
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pins {
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pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
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<STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
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<STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
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<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
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<STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
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<STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
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<STM32_PINMUX('A', 7, AF11)>, /* ETH_RMII_CRS_DV */
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<STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
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<STM32_PINMUX('C', 5, AF11)>; /* ETH_RMII_RXD1 */
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slew-rate = <2>;
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};
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};
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fmc_pins: fmc@0 {
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pins {
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pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
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<STM32_PINMUX('I', 9, AF12)>, /* D30 */
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<STM32_PINMUX('I', 7, AF12)>, /* D29 */
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<STM32_PINMUX('I', 6, AF12)>, /* D28 */
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<STM32_PINMUX('I', 3, AF12)>, /* D27 */
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<STM32_PINMUX('I', 2, AF12)>, /* D26 */
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<STM32_PINMUX('I', 1, AF12)>, /* D25 */
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<STM32_PINMUX('I', 0, AF12)>, /* D24 */
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<STM32_PINMUX('H',15, AF12)>, /* D23 */
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<STM32_PINMUX('H',14, AF12)>, /* D22 */
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<STM32_PINMUX('H',13, AF12)>, /* D21 */
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<STM32_PINMUX('H',12, AF12)>, /* D20 */
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<STM32_PINMUX('H',11, AF12)>, /* D19 */
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<STM32_PINMUX('H',10, AF12)>, /* D18 */
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<STM32_PINMUX('H', 9, AF12)>, /* D17 */
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<STM32_PINMUX('H', 8, AF12)>, /* D16 */
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<STM32_PINMUX('D',10, AF12)>, /* D15 */
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<STM32_PINMUX('D', 9, AF12)>, /* D14 */
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<STM32_PINMUX('D', 8, AF12)>, /* D13 */
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<STM32_PINMUX('E',15, AF12)>, /* D12 */
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<STM32_PINMUX('E',14, AF12)>, /* D11 */
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<STM32_PINMUX('E',13, AF12)>, /* D10 */
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<STM32_PINMUX('E',12, AF12)>, /* D9 */
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<STM32_PINMUX('E',11, AF12)>, /* D8 */
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<STM32_PINMUX('E',10, AF12)>, /* D7 */
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<STM32_PINMUX('E', 9, AF12)>, /* D6 */
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<STM32_PINMUX('E', 8, AF12)>, /* D5 */
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<STM32_PINMUX('E', 7, AF12)>, /* D4 */
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<STM32_PINMUX('D', 1, AF12)>, /* D3 */
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<STM32_PINMUX('D', 0, AF12)>, /* D2 */
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<STM32_PINMUX('D',15, AF12)>, /* D1 */
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<STM32_PINMUX('D',14, AF12)>, /* D0 */
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<STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
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<STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
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<STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
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<STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
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<STM32_PINMUX('G', 5, AF12)>, /* BA1 */
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<STM32_PINMUX('G', 4, AF12)>, /* BA0 */
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<STM32_PINMUX('G', 1, AF12)>, /* A11 */
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<STM32_PINMUX('G', 0, AF12)>, /* A10 */
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<STM32_PINMUX('F',15, AF12)>, /* A9 */
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<STM32_PINMUX('F',14, AF12)>, /* A8 */
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<STM32_PINMUX('F',13, AF12)>, /* A7 */
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<STM32_PINMUX('F',12, AF12)>, /* A6 */
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<STM32_PINMUX('F', 5, AF12)>, /* A5 */
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<STM32_PINMUX('F', 4, AF12)>, /* A4 */
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<STM32_PINMUX('F', 3, AF12)>, /* A3 */
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<STM32_PINMUX('F', 2, AF12)>, /* A2 */
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<STM32_PINMUX('F', 1, AF12)>, /* A1 */
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<STM32_PINMUX('F', 0, AF12)>, /* A0 */
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<STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
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<STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
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<STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
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<STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
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<STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
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<STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
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slew-rate = <2>;
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};
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};
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qspi_pins: qspi@0 {
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pins {
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pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */
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<STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
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<STM32_PINMUX('C', 9, AF9)>, /* BK1_IO0 */
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<STM32_PINMUX('C',10, AF9)>, /* BK1_IO1 */
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<STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
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<STM32_PINMUX('E', 2, AF9)>; /* BK1_IO2 */
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slew-rate = <2>;
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};
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};
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usart1_pins_a: usart1-0 {
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bootph-all;
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pins1 {
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bootph-all;
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};
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pins2 {
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bootph-all;
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};
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};
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};
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&qspi {
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reg = <0xa0001000 0x1000>, <0x90000000 0x4000000>;
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flash0: mx66l51235l@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <108000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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reg = <0>;
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};
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};
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