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94c30f9c8f
As explained in commit 3bedbcc3aa ("arm: mvebu: a38x: serdes: Don't
overwrite read-only SAR PCIe registers") it is required to set Maximum Link
Width bits of PCIe Root Port Link Capabilities Register depending of number
of used serdes lanes. As this register is part of PCIe address space and
not serdes address space, move it into pci_mvebu.c driver.
Read number of PCIe lanes from DT property "num-lanes" which is used also
by other PCIe controller drivers in Linux kernel. If this property is
absent then it defaults to 1. This property needs to be set to 4 for every
mvebu board which use PEX_ROOT_COMPLEX_X4 or PEX_BUS_MODE_X4.
Enabling of PCIe port needs to be done afer all registers in PCIe address
space are properly configure. For this purpose use new mvebu-reset driver
(part of system-controller) and remove this code from serdes code.
Because some PCIe ports cannot be enabled individually, it is required to
first setup all PCIe ports and then enable them.
This change contains also all required "num-lanes" and "resets" DTS
properties, to make pci_mvebu.c driver work correctly.
Signed-off-by: Pali Rohár <pali@kernel.org>
345 lines
7.3 KiB
Text
345 lines
7.3 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree Include file for Marvell 98dx3236 family SoC
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*
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* Copyright (C) 2016 Allied Telesis Labs
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*
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* Contains definitions specific to the 98dx3236 SoC that are not
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* common to all Armada XP SoCs.
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*/
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#include "armada-370-xp.dtsi"
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "Marvell 98DX3236 SoC";
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compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "marvell,98dx3236-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <0>;
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clocks = <&cpuclk 0>;
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clock-latency = <1000000>;
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};
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};
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soc {
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compatible = "marvell,armadaxp-mbus", "simple-bus";
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
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MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
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MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
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bootrom {
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compatible = "marvell,bootrom";
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reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
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};
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/*
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* 98DX3236 has 1 x1 PCIe unit Gen2.0
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*/
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pciec: pcie@82000000 {
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compatible = "marvell,armada-xp-pcie";
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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msi-parent = <&mpic>;
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bus-range = <0x00 0xff>;
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ranges =
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<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
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0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
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0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
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pcie1: pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 58>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 5>;
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resets = <&systemc 0 0>;
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status = "disabled";
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};
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};
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internal-regs {
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sdramc: sdramc@1400 {
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compatible = "marvell,armada-xp-sdram-controller";
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reg = <0x1400 0x500>;
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};
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L2: l2-cache@8000 {
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compatible = "marvell,aurora-system-cache";
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reg = <0x08000 0x1000>;
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cache-id-part = <0x100>;
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cache-level = <2>;
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cache-unified;
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wt-override;
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};
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gpio0: gpio@18100 {
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compatible = "marvell,orion-gpio";
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reg = <0x18100 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <82>, <83>, <84>, <85>;
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};
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/* does not exist */
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gpio1: gpio@18140 {
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compatible = "marvell,orion-gpio";
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reg = <0x18140 0x40>;
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status = "disabled";
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};
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gpio2: gpio@18180 { /* rework some properties */
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compatible = "marvell,orion-gpio";
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reg = <0x18180 0x40>;
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ngpios = <1>; /* only gpio #32 */
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <87>;
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};
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systemc: system-controller@18200 {
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compatible = "marvell,armada-370-xp-system-controller";
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reg = <0x18200 0x500>;
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#reset-cells = <2>;
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};
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gateclk: clock-gating-control@18220 {
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compatible = "marvell,mv98dx3236-gating-clock";
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reg = <0x18220 0x4>;
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clocks = <&coreclk 0>;
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#clock-cells = <1>;
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};
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cpuclk: clock-complex@18700 {
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#clock-cells = <1>;
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compatible = "marvell,mv98dx3236-cpu-clock";
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reg = <0x18700 0x24>, <0x1c054 0x10>;
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clocks = <&coreclk 1>;
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};
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corediv-clock@18740 {
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status = "disabled";
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};
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cpu-config@21000 {
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compatible = "marvell,armada-xp-cpu-config";
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reg = <0x21000 0x8>;
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};
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ethernet@70000 {
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compatible = "marvell,armada-xp-neta";
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};
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ethernet@74000 {
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compatible = "marvell,armada-xp-neta";
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};
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xor1: xor@f0800 {
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compatible = "marvell,orion-xor";
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reg = <0xf0800 0x100
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0xf0a00 0x100>;
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clocks = <&gateclk 22>;
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status = "okay";
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xor10 {
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interrupts = <51>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor11 {
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interrupts = <52>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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nand_controller: nand@d0000 {
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clocks = <&dfx_coredivclk 0>;
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};
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xor0: xor@f0900 {
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compatible = "marvell,orion-xor";
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reg = <0xF0900 0x100
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0xF0B00 0x100>;
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clocks = <&gateclk 28>;
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status = "okay";
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xor00 {
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interrupts = <94>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <95>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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};
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dfx: dfx-server@ac000000 {
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compatible = "marvell,dfx-server", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
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reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
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thermal: thermal@f8078 {
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compatible = "marvell,armada380-thermal";
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reg = <0xf8078 0x4>, <0xf8074 0x4>;
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status = "okay";
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};
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coreclk: mvebu-sar@f8204 {
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compatible = "marvell,mv98dx3236-core-clock";
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reg = <0xf8204 0x4>;
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#clock-cells = <1>;
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};
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dfx_coredivclk: corediv-clock@f8268 {
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compatible = "marvell,mv98dx3236-corediv-clock";
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reg = <0xf8268 0xc>;
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#clock-cells = <1>;
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clocks = <&mainpll>;
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clock-output-names = "nand";
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};
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};
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switch: switch@a8000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
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pp0: packet-processor@0 {
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compatible = "marvell,prestera-98dx3236", "marvell,prestera";
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reg = <0 0x4000000>;
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interrupts = <33>, <34>, <35>;
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dfx = <&dfx>;
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};
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};
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};
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clocks {
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/* 25 MHz reference crystal */
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refclk: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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};
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};
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&i2c0 {
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compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
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reg = <0x11000 0x100>;
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};
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&i2c1 {
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compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
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reg = <0x11100 0x100>;
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};
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&mpic {
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reg = <0x20a00 0x2d0>, <0x21070 0x58>;
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};
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&rtc {
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status = "disabled";
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};
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&timer {
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compatible = "marvell,armada-xp-timer";
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clocks = <&coreclk 2>, <&refclk>;
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clock-names = "nbclk", "fixed";
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};
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&watchdog {
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compatible = "marvell,armada-xp-wdt";
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clocks = <&coreclk 2>, <&refclk>;
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clock-names = "nbclk", "fixed";
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};
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&cpurst {
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reg = <0x20800 0x20>;
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};
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&usb0 {
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clocks = <&gateclk 18>;
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};
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&usb1 {
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clocks = <&gateclk 19>;
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};
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&pinctrl {
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compatible = "marvell,98dx3236-pinctrl";
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nand_pins: nand-pins {
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marvell,pins = "mpp20", "mpp21", "mpp22",
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"mpp23", "mpp24", "mpp25",
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"mpp26", "mpp27", "mpp28",
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"mpp29", "mpp30";
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marvell,function = "dev";
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};
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nand_rb: nand-rb {
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marvell,pins = "mpp19";
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marvell,function = "nand";
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};
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spi0_pins: spi0-pins {
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marvell,pins = "mpp0", "mpp1",
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"mpp2", "mpp3";
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marvell,function = "spi0";
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};
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};
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&spi0 {
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compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
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pinctrl-0 = <&spi0_pins>;
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pinctrl-names = "default";
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};
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&sdio {
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status = "disabled";
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};
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