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97405d843e
Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com>
261 lines
7.7 KiB
C
261 lines
7.7 KiB
C
/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Aneesh V <aneesh@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _CLOCKS_OMAP4_H_
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#define _CLOCKS_OMAP4_H_
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#include <common.h>
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#include <asm/omap_common.h>
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/*
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* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
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* loop, allow for a minimum of 2 ms wait (in reality the wait will be
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* much more than that)
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*/
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#define LDELAY 1000000
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/* CM_DLL_CTRL */
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#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
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#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
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#define CM_DLL_CTRL_NO_OVERRIDE 0
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/* CM_CLKMODE_DPLL */
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#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
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#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
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#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
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#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
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#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
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#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
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#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
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#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
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#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
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#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
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#define CM_CLKMODE_DPLL_EN_SHIFT 0
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#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
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#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
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#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
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#define DPLL_EN_STOP 1
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#define DPLL_EN_MN_BYPASS 4
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#define DPLL_EN_LOW_POWER_BYPASS 5
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#define DPLL_EN_FAST_RELOCK_BYPASS 6
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#define DPLL_EN_LOCK 7
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/* CM_IDLEST_DPLL fields */
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#define ST_DPLL_CLK_MASK 1
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/* CM_CLKSEL_DPLL */
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#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
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#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
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#define CM_CLKSEL_DPLL_M_SHIFT 8
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#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
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#define CM_CLKSEL_DPLL_N_SHIFT 0
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#define CM_CLKSEL_DPLL_N_MASK 0x7F
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#define CM_CLKSEL_DCC_EN_SHIFT 22
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#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
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/* CM_SYS_CLKSEL */
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#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
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/* CM_CLKSEL_CORE */
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#define CLKSEL_CORE_SHIFT 0
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#define CLKSEL_L3_SHIFT 4
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#define CLKSEL_L4_SHIFT 8
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#define CLKSEL_CORE_X2_DIV_1 0
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#define CLKSEL_L3_CORE_DIV_2 1
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#define CLKSEL_L4_L3_DIV_2 1
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/* CM_ABE_PLL_REF_CLKSEL */
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#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
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#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
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#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
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#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
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/* CM_BYPCLK_DPLL_IVA */
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#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
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#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
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#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
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/* CM_SHADOW_FREQ_CONFIG1 */
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#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
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#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
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#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
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#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
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#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
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#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
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#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
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/*CM_<clock_domain>__CLKCTRL */
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#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
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#define CD_CLKCTRL_CLKTRCTRL_MASK 3
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#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
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#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
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#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
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#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
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/* CM_<clock_domain>_<module>_CLKCTRL */
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#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
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#define MODULE_CLKCTRL_MODULEMODE_MASK 3
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#define MODULE_CLKCTRL_IDLEST_SHIFT 16
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#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
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#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
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#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
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#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
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#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
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#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
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#define MODULE_CLKCTRL_IDLEST_IDLE 2
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#define MODULE_CLKCTRL_IDLEST_DISABLED 3
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/* CM_L4PER_GPIO4_CLKCTRL */
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#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
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/* CM_L3INIT_HSMMCn_CLKCTRL */
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#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
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/* CM_WKUP_GPTIMER1_CLKCTRL */
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#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
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/* CM_CAM_ISS_CLKCTRL */
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#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
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/* CM_DSS_DSS_CLKCTRL */
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#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
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/* CM_L3INIT_USBPHY_CLKCTRL */
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#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
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/* CM_MPU_MPU_CLKCTRL */
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#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
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#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
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#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25
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#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
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/* Clock frequencies */
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#define OMAP_SYS_CLK_IND_38_4_MHZ 6
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/* PRM_VC_VAL_BYPASS */
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#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
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/* SMPS */
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#define SMPS_I2C_SLAVE_ADDR 0x12
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#define SMPS_REG_ADDR_VCORE1 0x55
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#define SMPS_REG_ADDR_VCORE2 0x5B
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#define SMPS_REG_ADDR_VCORE3 0x61
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#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
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#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
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/* TPS */
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#define TPS62361_I2C_SLAVE_ADDR 0x60
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#define TPS62361_REG_ADDR_SET0 0x0
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#define TPS62361_REG_ADDR_SET1 0x1
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#define TPS62361_REG_ADDR_SET2 0x2
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#define TPS62361_REG_ADDR_SET3 0x3
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#define TPS62361_REG_ADDR_CTRL 0x4
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#define TPS62361_REG_ADDR_TEMP 0x5
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#define TPS62361_REG_ADDR_RMP_CTRL 0x6
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#define TPS62361_REG_ADDR_CHIP_ID 0x8
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#define TPS62361_REG_ADDR_CHIP_ID_2 0x9
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#define TPS62361_BASE_VOLT_MV 500
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#define TPS62361_VSEL0_GPIO 7
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/* AUXCLKx reg fields */
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#define AUXCLK_ENABLE_MASK (1 << 8)
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#define AUXCLK_SRCSELECT_SHIFT 1
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#define AUXCLK_SRCSELECT_MASK (3 << 1)
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#define AUXCLK_CLKDIV_SHIFT 16
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#define AUXCLK_CLKDIV_MASK (0xF << 16)
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#define AUXCLK_SRCSELECT_SYS_CLK 0
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#define AUXCLK_SRCSELECT_CORE_DPLL 1
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#define AUXCLK_SRCSELECT_PER_DPLL 2
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#define AUXCLK_SRCSELECT_ALTERNATE 3
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#define AUXCLK_CLKDIV_2 1
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#define AUXCLK_CLKDIV_16 0xF
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/* ALTCLKSRC */
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#define ALTCLKSRC_MODE_MASK 3
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#define ALTCLKSRC_ENABLE_INT_MASK 4
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#define ALTCLKSRC_ENABLE_EXT_MASK 8
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#define ALTCLKSRC_MODE_ACTIVE 1
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#define DPLL_NO_LOCK 0
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#define DPLL_LOCK 1
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/* Clock Defines */
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#define V_OSCK 38400000 /* Clock output from T2 */
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#define V_SCLK V_OSCK
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struct omap4_scrm_regs {
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u32 revision; /* 0x0000 */
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u32 pad00[63];
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u32 clksetuptime; /* 0x0100 */
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u32 pmicsetuptime; /* 0x0104 */
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u32 pad01[2];
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u32 altclksrc; /* 0x0110 */
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u32 pad02[2];
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u32 c2cclkm; /* 0x011c */
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u32 pad03[56];
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u32 extclkreq; /* 0x0200 */
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u32 accclkreq; /* 0x0204 */
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u32 pwrreq; /* 0x0208 */
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u32 pad04[1];
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u32 auxclkreq0; /* 0x0210 */
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u32 auxclkreq1; /* 0x0214 */
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u32 auxclkreq2; /* 0x0218 */
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u32 auxclkreq3; /* 0x021c */
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u32 auxclkreq4; /* 0x0220 */
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u32 auxclkreq5; /* 0x0224 */
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u32 pad05[3];
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u32 c2cclkreq; /* 0x0234 */
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u32 pad06[54];
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u32 auxclk0; /* 0x0310 */
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u32 auxclk1; /* 0x0314 */
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u32 auxclk2; /* 0x0318 */
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u32 auxclk3; /* 0x031c */
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u32 auxclk4; /* 0x0320 */
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u32 auxclk5; /* 0x0324 */
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u32 pad07[54];
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u32 rsttime_reg; /* 0x0400 */
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u32 pad08[6];
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u32 c2crstctrl; /* 0x041c */
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u32 extpwronrstctrl; /* 0x0420 */
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u32 pad09[59];
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u32 extwarmrstst_reg; /* 0x0510 */
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u32 apewarmrstst_reg; /* 0x0514 */
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u32 pad10[1];
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u32 c2cwarmrstst_reg; /* 0x051C */
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};
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#endif /* _CLOCKS_OMAP4_H_ */
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