mirror of
https://github.com/AsahiLinux/u-boot
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Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
453 lines
14 KiB
C
453 lines
14 KiB
C
/*
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* (C) Copyright 2006-2008
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* Texas Instruments.
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <x0khasim@ti.com>
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*
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* Configuration settings for the TI OMAP3530 Beagle board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_OMAP 1 /* in a TI OMAP core */
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#define CONFIG_OMAP34XX 1 /* which is a 34XX */
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#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
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#define CONFIG_OMAP_GPIO
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#define CONFIG_SDRC /* The chip has SDRC controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap3.h>
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/*
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* Display CPU and Board information
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*/
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#define CONFIG_DISPLAY_CPUINFO 1
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#define CONFIG_DISPLAY_BOARDINFO 1
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/* Clock Defines */
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#define V_OSCK 26000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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#undef CONFIG_USE_IRQ /* no support for IRQs */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_REVISION_TAG 1
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
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/* Sector */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
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/*
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* Hardware drivers
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*/
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/*
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* NS16550 Configuration
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*/
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#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
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/*
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* select serial console configuration
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*/
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#define CONFIG_CONS_INDEX 3
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#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
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#define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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#define CONFIG_GENERIC_MMC 1
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#define CONFIG_MMC 1
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#define CONFIG_OMAP_HSMMC 1
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#define CONFIG_DOS_PARTITION 1
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/* Status LED */
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#define CONFIG_STATUS_LED 1
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#define CONFIG_BOARD_SPECIFIC_LED 1
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#define STATUS_LED_BIT 0x01
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#define STATUS_LED_STATE STATUS_LED_ON
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#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
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#define STATUS_LED_BIT1 0x02
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#define STATUS_LED_STATE1 STATUS_LED_ON
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#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
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#define STATUS_LED_BOOT STATUS_LED_BIT
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#define STATUS_LED_GREEN STATUS_LED_BIT1
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/* Enable Multi Bus support for I2C */
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#define CONFIG_I2C_MULTI_BUS 1
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/* Probe all devices */
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#define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}}
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/* USB */
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#define CONFIG_MUSB_UDC 1
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#define CONFIG_USB_OMAP3 1
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#define CONFIG_TWL4030_USB 1
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/* USB device configuration */
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#define CONFIG_USB_DEVICE 1
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#define CONFIG_USB_TTY 1
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
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/* USB EHCI */
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#define CONFIG_CMD_USB
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_OMAP
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/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */
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#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
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#define CONFIG_USB_ULPI
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#define CONFIG_USB_ULPI_VIEWPORT_OMAP
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#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_SMSC95XX
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#define CONFIG_USB_ETHER_ASIX
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/* commands to include */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_EXT2 /* EXT2 Support */
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#define CONFIG_CMD_FAT /* FAT support */
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#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
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#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
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#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
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#define MTDIDS_DEFAULT "nand0=nand"
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#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
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"1920k(u-boot),128k(u-boot-env),"\
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"4m(kernel),-(fs)"
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#define CONFIG_CMD_I2C /* I2C serial bus support */
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#define CONFIG_CMD_MMC /* MMC support */
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#define CONFIG_USB_STORAGE /* USB storage support */
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#define CONFIG_CMD_NAND /* NAND support */
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#define CONFIG_CMD_LED /* LED support */
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#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
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#define CONFIG_CMD_NFS /* NFS support */
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_SETEXPR /* Evaluate expressions */
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#define CONFIG_CMD_GPIO /* Enable gpio command */
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#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
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#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
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#undef CONFIG_CMD_IMI /* iminfo */
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#undef CONFIG_CMD_IMLS /* List all found images */
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_HARD_I2C 1
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 1
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#define CONFIG_SYS_I2C_BUS 0
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#define CONFIG_SYS_I2C_BUS_SELECT 1
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#define CONFIG_I2C_MULTI_BUS 1
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#define CONFIG_DRIVER_OMAP34XX_I2C 1
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#define CONFIG_VIDEO_OMAP3 /* DSS Support */
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/*
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* TWL4030
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*/
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#define CONFIG_TWL4030_POWER 1
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#define CONFIG_TWL4030_LED 1
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/*
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* Board NAND Info.
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*/
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#define CONFIG_SYS_NAND_QUIET_TEST 1
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
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/* to access nand */
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access nand at */
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/* CS0 */
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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#define CONFIG_JFFS2_NAND
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/* nand device jffs2 lives on */
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#define CONFIG_JFFS2_DEV "nand0"
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/* start of jffs2 partition */
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#define CONFIG_JFFS2_PART_OFFSET 0x680000
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#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
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/* partition */
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/* Environment information */
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x80200000\0" \
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"rdaddr=0x81000000\0" \
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"usbtty=cdc_acm\0" \
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"bootfile=uImage.beagle\0" \
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"console=ttyO2,115200n8\0" \
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"mpurate=auto\0" \
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"buddy=none\0" \
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"optargs=\0" \
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"camera=none\0" \
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"vram=12M\0" \
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"dvimode=640x480MR-16@60\0" \
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"defaultdisplay=dvi\0" \
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"mmcdev=0\0" \
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"mmcroot=/dev/mmcblk0p2 rw\0" \
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"mmcrootfstype=ext3 rootwait\0" \
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"nandroot=ubi0:rootfs ubi.mtd=4\0" \
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"nandrootfstype=ubifs\0" \
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"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
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"ramrootfstype=ext2\0" \
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"mmcargs=setenv bootargs console=${console} " \
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"${optargs} " \
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"mpurate=${mpurate} " \
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"buddy=${buddy} "\
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"camera=${camera} "\
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"vram=${vram} " \
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"omapfb.mode=dvi:${dvimode} " \
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"omapdss.def_disp=${defaultdisplay} " \
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"root=${mmcroot} " \
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"rootfstype=${mmcrootfstype}\0" \
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"nandargs=setenv bootargs console=${console} " \
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"${optargs} " \
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"mpurate=${mpurate} " \
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"buddy=${buddy} "\
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"camera=${camera} "\
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"vram=${vram} " \
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"omapfb.mode=dvi:${dvimode} " \
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"omapdss.def_disp=${defaultdisplay} " \
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"root=${nandroot} " \
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"rootfstype=${nandrootfstype}\0" \
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"bootenv=uEnv.txt\0" \
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"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
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"importbootenv=echo Importing environment from mmc ...; " \
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"env import -t $loadaddr $filesize\0" \
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"ramargs=setenv bootargs console=${console} " \
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"${optargs} " \
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"mpurate=${mpurate} " \
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"buddy=${buddy} "\
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"vram=${vram} " \
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"omapfb.mode=dvi:${dvimode} " \
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"omapdss.def_disp=${defaultdisplay} " \
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"root=${ramroot} " \
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"rootfstype=${ramrootfstype}\0" \
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"loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
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"loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
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"loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} /boot/uImage\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"bootm ${loadaddr}\0" \
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"nandboot=echo Booting from nand ...; " \
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"run nandargs; " \
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"nand read ${loadaddr} 280000 400000; " \
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"bootm ${loadaddr}\0" \
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"ramboot=echo Booting from ramdisk ...; " \
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"run ramargs; " \
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"bootm ${loadaddr}\0" \
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"userbutton=if gpio input 173; then run userbutton_xm; " \
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"else run userbutton_nonxm; fi;\0" \
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"userbutton_xm=gpio input 4;\0" \
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"userbutton_nonxm=gpio input 7;\0"
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/* "run userbutton" will return 1 (false) if is pressed and 0 (false) if not */
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#define CONFIG_BOOTCOMMAND \
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"if mmc rescan ${mmcdev}; then " \
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"if run userbutton; then " \
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"setenv bootenv uEnv.txt;" \
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"else " \
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"setenv bootenv user.txt;" \
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"fi;" \
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"echo SD/MMC found on device ${mmcdev};" \
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"if run loadbootenv; then " \
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"echo Loaded environment from ${bootenv};" \
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"run importbootenv;" \
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"fi;" \
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"if test -n $uenvcmd; then " \
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"echo Running uenvcmd ...;" \
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"run uenvcmd;" \
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"fi;" \
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"if run loaduimage; then " \
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"run mmcboot;" \
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"fi;" \
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"fi;" \
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"run nandboot;" \
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#define CONFIG_AUTO_COMPLETE 1
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # "
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
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#define CONFIG_SYS_ALT_MEMTEST 1
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#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
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/* defaults */
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#define CONFIG_SYS_MEMTEST_END (0x87FFFFFF) /* 128MB */
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#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
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#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
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/* load address */
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/*
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* OMAP3 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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#define CONFIG_SYS_HZ 1000
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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/* **** PISMO SUPPORT *** */
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/* Configure the PISMO */
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#define PISMO1_NAND_SIZE GPMC_SIZE_128M
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#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
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#if defined(CONFIG_CMD_NAND)
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#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
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#endif
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/* Monitor at start of flash */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
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#define CONFIG_ENV_IS_IN_NAND 1
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#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
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#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
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#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
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#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
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#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
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#define CONFIG_SYS_INIT_RAM_SIZE 0x800
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_OMAP3_SPI
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#define CONFIG_SYS_CACHELINE_SIZE 64
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/* Defines for SPL */
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#define CONFIG_SPL
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_TEXT_BASE 0x40200800
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#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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#define CONFIG_SPL_BSS_START_ADDR 0x80000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
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#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
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#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
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#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBDISK_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_FAT_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_GPIO_SUPPORT
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#define CONFIG_SPL_POWER_SUPPORT
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#define CONFIG_SPL_OMAP3_ID_NAND
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#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
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/* NAND boot config */
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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/*
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* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
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* 64 bytes before this address should be set aside for u-boot.img's
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* header. That is 0x800FFFC0--0x80100000 should not be used for any
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* other needs.
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*/
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#define CONFIG_SYS_TEXT_BASE 0x80100000
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#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#endif /* __CONFIG_H */
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