mirror of
https://github.com/AsahiLinux/u-boot
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7e514eef02
This patch does 3 things: 1. Enables ECC by setting 21st bit of L2CTLR. 2. Restore data and tag RAM latencies to 3 cycles because iROM sets 0x3000400 L2CTLR value during switching. 3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR. We need to restore this here due to switching. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
76 lines
1.7 KiB
C
76 lines
1.7 KiB
C
/*
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* Copyright (c) 2010 Samsung Electronics.
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* Minkyu Kang <mk7.kang@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/system.h>
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enum l2_cache_params {
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CACHE_TAG_RAM_SETUP = (1 << 9),
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CACHE_DATA_RAM_SETUP = (1 << 5),
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CACHE_TAG_RAM_LATENCY = (2 << 6),
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CACHE_DATA_RAM_LATENCY = (2 << 0),
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CACHE_ENABLE_CLEAN_EVICT = (0 << 3),
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CACHE_DISABLE_CLEAN_EVICT = (1 << 3)
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};
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void reset_cpu(ulong addr)
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{
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writel(0x1, samsung_get_base_swreset());
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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#ifndef CONFIG_SYS_L2CACHE_OFF
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/*
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* Set L2 cache parameters
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*/
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static void exynos5_set_l2cache_params(void)
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{
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unsigned int l2ctlr = 0, l2actlr = 0;
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/* Read L2CTLR value */
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asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(l2ctlr));
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/* Set cache latency cycles */
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l2ctlr |= CACHE_TAG_RAM_LATENCY |
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CACHE_DATA_RAM_LATENCY;
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if (proid_is_exynos5420() || proid_is_exynos5800()) {
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/* Read L2ACTLR value */
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asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (l2actlr));
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/* Disable clean/evict push to external */
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l2actlr |= CACHE_DISABLE_CLEAN_EVICT;
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/* Write new vlaue to L2ACTLR */
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asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (l2actlr));
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} else {
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/* Set cache setup cycles */
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l2ctlr |= CACHE_TAG_RAM_SETUP |
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CACHE_DATA_RAM_SETUP;
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}
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/* Write new vlaue to L2CTLR */
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asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(l2ctlr));
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}
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/*
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* Sets L2 cache related parameters before enabling data cache
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*/
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void v7_outer_cache_enable(void)
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{
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if (cpu_is_exynos5())
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exynos5_set_l2cache_params();
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}
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#endif
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