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b40f734af9
T114 needs the SYSCTR0 counter initialized so the TSC can be read by the kernel. Do it in the bootloader since it's a write-once deal (secure/non-secure mode dependent). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
35 lines
1.3 KiB
C
35 lines
1.3 KiB
C
/*
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _TEGRA114_SYSCTR_H_
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#define _TEGRA114_SYSCTR_H_
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struct sysctr_ctlr {
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u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */
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u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */
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u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
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u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
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u32 reserved1[4]; /* 0x10 - 0x1C */
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u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
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u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */
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u32 reserved2[1002]; /* 0x28 - 0xFCC */
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u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */
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};
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#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */
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#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */
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#endif /* _TEGRA114_SYSCTR_H_ */
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