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174d728471
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
127 lines
3 KiB
C
127 lines
3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 - 2018 Xilinx, Inc.
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* Michal Simek <michal.simek@amd.com>
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/armv8/mmu.h>
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#include <asm/cache.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/cache.h>
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#include <dm/platdata.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define VERSAL_MEM_MAP_USED 5
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#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
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#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
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#define TCM_MAP 1
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#else
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#define TCM_MAP 0
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#endif
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/* +1 is end of list which needs to be empty */
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#define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
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static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
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{
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x70000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0xf0000000UL,
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.phys = 0xf0000000UL,
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.size = 0x0fe00000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x400000000UL,
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.phys = 0x400000000UL,
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.size = 0x200000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x600000000UL,
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.phys = 0x600000000UL,
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.size = 0x800000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xe00000000UL,
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.phys = 0xe00000000UL,
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.size = 0xf200000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}
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};
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void mem_map_fill(void)
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{
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int banks = VERSAL_MEM_MAP_USED;
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#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
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versal_mem_map[banks].virt = 0xffe00000UL;
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versal_mem_map[banks].phys = 0xffe00000UL;
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versal_mem_map[banks].size = 0x00200000UL;
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versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE;
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banks = banks + 1;
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#endif
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for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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/* Zero size means no more DDR that's this is end */
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if (!gd->bd->bi_dram[i].size)
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break;
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#if defined(CONFIG_VERSAL_NO_DDR)
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if (gd->bd->bi_dram[i].start < 0x80000000UL ||
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gd->bd->bi_dram[i].start > 0x100000000UL) {
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printf("Ignore caches over %llx/%llx\n",
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gd->bd->bi_dram[i].start,
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gd->bd->bi_dram[i].size);
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continue;
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}
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#endif
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versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
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versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
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versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
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versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE;
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banks = banks + 1;
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}
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}
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struct mm_region *mem_map = versal_mem_map;
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u64 get_page_table_size(void)
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{
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return 0x14000;
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}
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#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU)
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int arm_reserve_mmu(void)
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{
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tcm_init(TCM_LOCK);
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gd->arch.tlb_size = PGTABLE_SIZE;
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gd->arch.tlb_addr = VERSAL_TCM_BASE_ADDR;
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return 0;
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}
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#endif
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U_BOOT_DRVINFO(soc_xilinx_versal) = {
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.name = "soc_xilinx_versal",
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};
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