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https://github.com/AsahiLinux/u-boot
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2aee173ba0
This function is the same for each device when it needs to shutdown the R5 core. Move this to the common section and move the remaining device specific ID list to the device hardware include. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
60 lines
1.8 KiB
C
60 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* K3: J721E SoC definitions, structures etc.
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*
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* (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#ifndef __ASM_ARCH_J721E_HARDWARE_H
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#define __ASM_ARCH_J721E_HARDWARE_H
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#include <config.h>
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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#define WKUP_CTRL_MMR0_BASE 0x43000000
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#define MCU_CTRL_MMR0_BASE 0x40f00000
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#define CTRL_MMR0_BASE 0x00100000
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#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
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#define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0)
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#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0
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#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1)
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#define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 1
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#define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK BIT(6)
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#define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT 6
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#define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7)
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#define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7
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#define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
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#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3)
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#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
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#define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6)
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#define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6
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/* ROM HANDOFF Structure location */
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#define ROM_EXTENDED_BOOT_DATA_INFO 0x41cffb00
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/* MCU SCRATCHPAD usage */
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#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
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#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
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#define J721E_DEV_MCU_RTI0 262
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#define J721E_DEV_MCU_RTI1 263
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#define J721E_DEV_MCU_ARMSS0_CPU0 250
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#define J721E_DEV_MCU_ARMSS0_CPU1 251
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static const u32 put_device_ids[] = {
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J721E_DEV_MCU_RTI0,
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J721E_DEV_MCU_RTI1,
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};
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static const u32 put_core_ids[] = {
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J721E_DEV_MCU_ARMSS0_CPU1,
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J721E_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
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};
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#endif
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#endif /* __ASM_ARCH_J721E_HARDWARE_H */
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