mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-02 09:30:10 +00:00
48a33645b0
P2041 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
99 lines
2.5 KiB
Text
99 lines
2.5 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
|
/*
|
|
* P2041 Silicon/SoC Device Tree Source (pre include)
|
|
*
|
|
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
|
|
* Copyright 2019 NXP
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
/include/ "e500mc_power_isa.dtsi"
|
|
|
|
/ {
|
|
compatible = "fsl,P2041";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
interrupt-parent = <&mpic>;
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: PowerPC,e500mc@0 {
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
fsl,portid-mapping = <0x80000000>;
|
|
};
|
|
cpu1: PowerPC,e500mc@1 {
|
|
device_type = "cpu";
|
|
reg = <1>;
|
|
fsl,portid-mapping = <0x40000000>;
|
|
};
|
|
cpu2: PowerPC,e500mc@2 {
|
|
device_type = "cpu";
|
|
reg = <2>;
|
|
fsl,portid-mapping = <0x20000000>;
|
|
};
|
|
cpu3: PowerPC,e500mc@3 {
|
|
device_type = "cpu";
|
|
reg = <3>;
|
|
fsl,portid-mapping = <0x10000000>;
|
|
};
|
|
};
|
|
|
|
soc: soc@ffe000000 {
|
|
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
|
reg = <0xf 0xfe000000 0 0x00001000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
device_type = "soc";
|
|
compatible = "simple-bus";
|
|
|
|
mpic: pic@40000 {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <4>;
|
|
reg = <0x40000 0x40000>;
|
|
compatible = "fsl,mpic", "chrp,open-pic";
|
|
device_type = "open-pic";
|
|
clock-frequency = <0x0>;
|
|
};
|
|
};
|
|
|
|
pcie@ffe200000 {
|
|
compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
|
|
reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
|
|
law_trgt_if = <0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
|
|
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
|
|
};
|
|
|
|
pcie@ffe201000 {
|
|
compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
|
|
reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
|
|
law_trgt_if = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
|
|
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
|
|
};
|
|
|
|
pcie@ffe202000 {
|
|
compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
|
|
reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
|
|
law_trgt_if = <2>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
|
|
0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
|
|
};
|
|
};
|