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7d7bb99e22
Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with an integrated CPU (referred to as the CnM block in Marvell's documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support has been ported from Marvell's SDK which is based on a much older version of U-Boot. Signed-off-by: Chris Packham <judge.packham@gmail.com>
124 lines
2.1 KiB
C
124 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <linux/libfdt.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/arch/cpu.h>
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#include <linux/sizes.h>
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#include <asm/armv8/mmu.h>
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#include "soc.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define RAM_SIZE SZ_1G
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static struct mm_region ac5_mem_map[] = {
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{
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/* RAM */
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.phys = CONFIG_SYS_SDRAM_BASE,
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.virt = CONFIG_SYS_SDRAM_BASE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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},
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{
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/* MMIO regions */
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.phys = 0x00000000,
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.virt = 0xa0000000,
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.size = 0x100000,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{
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/* MMIO regions */
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.phys = 0x100000,
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.virt = 0x100000,
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.size = 0x3ff00000,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{
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/* MMIO regions */
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.phys = 0x7F000000,
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.virt = 0x7F000000,
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.size = 0x21000000,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{
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0,
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}
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};
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struct mm_region *mem_map = ac5_mem_map;
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void reset_cpu(void)
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{
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}
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int print_cpuinfo(void)
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{
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soc_print_device_info();
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soc_print_clock_info();
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return 0;
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}
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int alleycat5_dram_init(void)
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{
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#define SCRATCH_PAD_REG 0x80010018
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int ret;
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/* override DDR_FW size if DTS is set with size */
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ret = fdtdec_setup_mem_size_base();
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if (ret == -EINVAL)
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gd->ram_size = readl(SCRATCH_PAD_REG) * 4ULL;
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/* if DRAM size == 0, print error message */
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if (gd->ram_size == 0) {
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pr_err("DRAM size not initialized - check DRAM configuration\n");
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printf("\n Using temporary DRAM size of 512MB.\n\n");
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gd->ram_size = SZ_512M;
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}
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ac5_mem_map[0].size = gd->ram_size;
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return 0;
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}
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int alleycat5_dram_init_banksize(void)
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{
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/*
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* Config single DRAM bank
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*/
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = gd->ram_size;
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return 0;
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}
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int timer_init(void)
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{
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return 0;
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}
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/*
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* get_ref_clk
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*
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* return: reference clock in MHz
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*/
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u32 get_ref_clk(void)
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{
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return 25;
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}
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