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https://github.com/AsahiLinux/u-boot
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10bc132510
This patch fixes configuring FIFOs for one-directional endpoints which have only one queue (either RX or TX, but noth both). Size of FIFO buffer is 2^(idx+3) bytes and starting address is 2^(addr+3). Moreover first 64 bytes are reserved for EP0. Without this patch if FIFO size specified by caller was zero then idx was incorrectly calculated (expr. ffs(0)-1) and size overflowed in fifosz register. This register uses has only 4 bits for FIFO size. Moreover specifying zero buffer size is not possible (with idx=0 is minimal buffer size 8 bytes). So even for one-directional endpoints we need to correctly specify both (RX and TX) FIFO buffer sizes and its addresses. This patch is fixing calculation of start address and buffer size to minimal value and ensures that it would not overlap with buffer reserved for EP0. This issue caused loose of packets on USB bus in both directions and basically usbtty was unusable. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Lukasz Majewski <lukma@denx.de> Acked-by: Pavel Machek <pavel@ucw.cz>
151 lines
3.8 KiB
C
151 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Mentor USB OTG Core functionality common for both Host and Device
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* functionality.
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*
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* Copyright (c) 2008 Texas Instruments
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*
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* Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
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*/
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#include <common.h>
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#include <linux/bitops.h>
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#include "musb_core.h"
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struct musb_regs *musbr;
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/*
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* program the mentor core to start (enable interrupts, dma, etc.)
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*/
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void musb_start(void)
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{
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#if defined(CONFIG_USB_MUSB_HCD)
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u8 devctl;
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u8 busctl;
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#endif
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/* disable all interrupts */
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writew(0, &musbr->intrtxe);
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writew(0, &musbr->intrrxe);
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writeb(0, &musbr->intrusbe);
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writeb(0, &musbr->testmode);
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/* put into basic highspeed mode and start session */
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writeb(MUSB_POWER_HSENAB, &musbr->power);
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#if defined(CONFIG_USB_MUSB_HCD)
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/* Program PHY to use EXT VBUS if required */
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if (musb_cfg.extvbus == 1) {
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busctl = musb_read_ulpi_buscontrol(musbr);
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musb_write_ulpi_buscontrol(musbr, busctl | ULPI_USE_EXTVBUS);
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}
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devctl = readb(&musbr->devctl);
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writeb(devctl | MUSB_DEVCTL_SESSION, &musbr->devctl);
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#endif
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}
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#ifdef MUSB_NO_DYNAMIC_FIFO
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# define config_fifo(dir, idx, addr)
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#else
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# define config_fifo(dir, idx, addr) \
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do { \
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writeb(idx, &musbr->dir##fifosz); \
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writew(addr, &musbr->dir##fifoadd); \
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} while (0)
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#endif
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/*
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* This function configures the endpoint configuration. The musb hcd or musb
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* device implementation can use this function to configure the endpoints
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* and set the FIFO sizes. Note: The summation of FIFO sizes of all endpoints
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* should not be more than the available FIFO size.
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*
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* epinfo - Pointer to EP configuration table
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* cnt - Number of entries in the EP conf table.
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*/
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void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt)
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{
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u16 csr;
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u16 fifoaddr = 64 >> 3; /* First 64 bytes of FIFO reserved for EP0 */
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u32 fifosize;
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u8 idx;
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while (cnt--) {
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/* prepare fifosize to write to register */
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fifosize = epinfo->epsize >> 3;
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idx = fifosize ? ((ffs(fifosize) - 1) & 0xF) : 0;
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writeb(epinfo->epnum, &musbr->index);
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if (epinfo->epdir) {
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/* Configure fifo size and fifo base address */
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config_fifo(tx, idx, fifoaddr);
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csr = readw(&musbr->txcsr);
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/* clear the data toggle bit */
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writew(csr | MUSB_TXCSR_CLRDATATOG, &musbr->txcsr);
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/* Flush fifo if required */
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if (csr & MUSB_TXCSR_TXPKTRDY)
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writew(csr | MUSB_TXCSR_FLUSHFIFO,
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&musbr->txcsr);
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} else {
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/* Configure fifo size and fifo base address */
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config_fifo(rx, idx, fifoaddr);
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csr = readw(&musbr->rxcsr);
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/* clear the data toggle bit */
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writew(csr | MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr);
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/* Flush fifo if required */
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if (csr & MUSB_RXCSR_RXPKTRDY)
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writew(csr | MUSB_RXCSR_FLUSHFIFO,
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&musbr->rxcsr);
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}
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fifoaddr += 1 << idx;
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epinfo++;
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}
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}
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/*
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* This function writes data to endpoint fifo
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*
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* ep - endpoint number
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* length - number of bytes to write to FIFO
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* fifo_data - Pointer to data buffer that contains the data to write
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*/
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__attribute__((weak))
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void write_fifo(u8 ep, u32 length, void *fifo_data)
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{
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u8 *data = (u8 *)fifo_data;
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/* select the endpoint index */
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writeb(ep, &musbr->index);
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/* write the data to the fifo */
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while (length--)
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writeb(*data++, &musbr->fifox[ep]);
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}
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/*
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* AM35x supports only 32bit read operations so
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* use seperate read_fifo() function for it.
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*/
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#ifndef CONFIG_USB_AM35X
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/*
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* This function reads data from endpoint fifo
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*
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* ep - endpoint number
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* length - number of bytes to read from FIFO
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* fifo_data - pointer to data buffer into which data is read
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*/
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__attribute__((weak))
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void read_fifo(u8 ep, u32 length, void *fifo_data)
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{
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u8 *data = (u8 *)fifo_data;
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/* select the endpoint index */
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writeb(ep, &musbr->index);
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/* read the data to the fifo */
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while (length--)
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*data++ = readb(&musbr->fifox[ep]);
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}
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#endif /* CONFIG_USB_AM35X */
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