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https://github.com/AsahiLinux/u-boot
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7d559604d0
PPA binary needs to be relocated on secure DDR, hence marking out a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag is set Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
116 lines
2.4 KiB
C
116 lines
2.4 KiB
C
/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include <hwconfig.h>
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#include <environment.h>
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#include <fsl_mmdc.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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puts("Board: LS1012AFRDM ");
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return 0;
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}
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int dram_init(void)
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{
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static const struct fsl_mmdc_info mparam = {
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0x04180000, /* mdctl */
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0x00030035, /* mdpdc */
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0x12554000, /* mdotc */
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0xbabf7954, /* mdcfg0 */
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0xdb328f64, /* mdcfg1 */
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0x01ff00db, /* mdcfg2 */
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0x00001680, /* mdmisc */
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0x0f3c8000, /* mdref */
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0x00002000, /* mdrwd */
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0x00bf1023, /* mdor */
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0x0000003f, /* mdasp */
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0x0000022a, /* mpodtctrl */
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0xa1390003, /* mpzqhwctrl */
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};
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mmdc_init(&mparam);
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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int board_early_init_f(void)
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{
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fsl_lsch2_early_init_f();
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return 0;
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}
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int board_init(void)
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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/*
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* Set CCI-400 control override register to enable barrier
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* transaction
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*/
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
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#ifdef CONFIG_ENV_IS_NOWHERE
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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return 0;
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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arch_fixup_fdt(blob);
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ft_cpu_setup(blob, bd);
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return 0;
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}
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void dram_init_banksize(void)
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{
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/*
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* gd->arch.secure_ram tracks the location of secure memory.
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* It was set as if the memory starts from 0.
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* The address needs to add the offset of its bank.
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*/
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
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gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
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gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
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gd->bd->bi_dram[1].size = gd->ram_size -
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CONFIG_SYS_DDR_BLOCK1_SIZE;
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#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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gd->arch.secure_ram = gd->bd->bi_dram[1].start +
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gd->arch.secure_ram -
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CONFIG_SYS_DDR_BLOCK1_SIZE;
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gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
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#endif
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} else {
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gd->bd->bi_dram[0].size = gd->ram_size;
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#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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gd->arch.secure_ram = gd->bd->bi_dram[0].start +
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gd->arch.secure_ram;
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gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
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#endif
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}
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}
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