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https://github.com/AsahiLinux/u-boot
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0017931971
Per a request from Andre Przywara and agreed with by Peter Hoyes, the vexpress aemv8r support wasn't quite ready to be merged, but the discussion had moved off list. We should keep the first patch in the series for now, but revert the rest. This reverts the following commits:e0bd6f31cedoc: Add documentation for the Arm vexpress board configs30e5a449e8arm: Use armv8_switch_to_el1 env to switch to EL1b53bbca63bvexpress64: Add BASER_FVP vexpress board variant2f5b7b7490armv8: Add ARMv8 MPU configuration logic37a757e227armv8: Ensure EL1&0 VMSA is enabled Signed-off-by: Tom Rini <trini@konsulko.com>
233 lines
7.1 KiB
C
233 lines
7.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuration for Versatile Express. Parts were derived from other ARM
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* configurations.
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*/
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#ifndef __VEXPRESS_AEMV8A_H
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#define __VEXPRESS_AEMV8A_H
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#define CONFIG_REMAKE_ELF
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/* Link Definitions */
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#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
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/* ATF loads u-boot here for BASE_FVP model */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
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#elif CONFIG_TARGET_VEXPRESS64_JUNO
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
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#endif
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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/* CS register bases for the original memory map. */
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#define V2M_PA_CS0 0x00000000
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#define V2M_PA_CS1 0x14000000
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#define V2M_PA_CS2 0x18000000
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#define V2M_PA_CS3 0x1c000000
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#define V2M_PA_CS4 0x0c000000
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#define V2M_PA_CS5 0x10000000
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#define V2M_PERIPH_OFFSET(x) (x << 16)
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#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
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#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
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#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
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#define V2M_BASE 0x80000000
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/* Common peripherals relative to CS7. */
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#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
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#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
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#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
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#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
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#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
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#define V2M_UART0 0x7ff80000
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#define V2M_UART1 0x7ff70000
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#else /* Not Juno */
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#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
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#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
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#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
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#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
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#endif
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#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
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#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
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#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
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#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
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#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
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#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
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#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
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/* System register offsets. */
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#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
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#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
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#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY 24000000 /* 24MHz */
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/* Generic Interrupt Controller Definitions */
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#ifdef CONFIG_GICV3
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#define GICD_BASE (0x2f000000)
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#define GICR_BASE (0x2f100000)
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#else
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#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
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#define GICD_BASE (0x2f000000)
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#define GICC_BASE (0x2c000000)
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#elif CONFIG_TARGET_VEXPRESS64_JUNO
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#define GICD_BASE (0x2C010000)
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#define GICC_BASE (0x2C02f000)
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#endif
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#endif /* !CONFIG_GICV3 */
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#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
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/* The Vexpress64 simulators use SMSC91C111 */
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#define CONFIG_SMC91111 1
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#define CONFIG_SMC91111_BASE (0x01A000000)
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#endif
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/* PL011 Serial Configuration */
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#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
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#define CONFIG_PL011_CLOCK 7372800
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#else
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#define CONFIG_PL011_CLOCK 24000000
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#endif
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/* BOOTP options */
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#define CONFIG_BOOTP_BOOTFILESIZE
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/* Miscellaneous configurable options */
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/* Physical Memory Map */
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#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
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/* Top 16MB reserved for secure world use */
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#define DRAM_SEC_SIZE 0x01000000
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#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
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#define PHYS_SDRAM_2 (0x880000000)
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#define PHYS_SDRAM_2_SIZE 0x180000000
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#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP && CONFIG_NR_DRAM_BANKS == 2
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#define PHYS_SDRAM_2 (0x880000000)
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#define PHYS_SDRAM_2_SIZE 0x80000000
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#endif
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/* Enable memtest */
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/* Initial environment variables */
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#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
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/* Copy the kernel and FDT to DRAM memory and boot */
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#define BOOTENV_DEV_AFS(devtypeu, devtypel, instance) \
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"bootcmd_afs=" \
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"afs load ${kernel_name} ${kernel_addr_r} ;"\
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"if test $? -eq 1; then "\
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" echo Loading ${kernel_alt_name} instead of ${kernel_name}; "\
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" afs load ${kernel_alt_name} ${kernel_addr_r};"\
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"fi ; "\
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"afs load ${fdtfile} ${fdt_addr_r} ;"\
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"if test $? -eq 1; then "\
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" echo Loading ${fdt_alt_name} instead of ${fdtfile}; "\
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" afs load ${fdt_alt_name} ${fdt_addr_r}; "\
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"fi ; "\
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"fdt addr ${fdt_addr_r}; fdt resize; " \
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"if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\
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"then "\
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" setenv ramdisk_param ${ramdisk_addr_r}; "\
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"else "\
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" setenv ramdisk_param -; "\
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"fi ; " \
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"booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}\0"
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#define BOOTENV_DEV_NAME_AFS(devtypeu, devtypel, instance) "afs "
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#define BOOT_TARGET_DEVICES(func) \
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func(USB, usb, 0) \
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func(SATA, sata, 0) \
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func(SATA, sata, 1) \
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func(PXE, pxe, na) \
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func(DHCP, dhcp, na) \
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func(AFS, afs, na)
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#include <config_distro_bootcmd.h>
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/*
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* Defines where the kernel and FDT exist in NOR flash and where it will
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* be copied into DRAM
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"kernel_name=norkern\0" \
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"kernel_alt_name=Image\0" \
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"kernel_addr_r=0x80080000\0" \
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"ramdisk_name=ramdisk.img\0" \
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"ramdisk_addr_r=0x88000000\0" \
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"fdtfile=board.dtb\0" \
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"fdt_alt_name=juno\0" \
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"fdt_addr_r=0x80000000\0" \
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BOOTENV
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#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"kernel_name=Image\0" \
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"kernel_addr=0x80080000\0" \
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"initrd_name=ramdisk.img\0" \
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"initrd_addr=0x88000000\0" \
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"fdtfile=devtree.dtb\0" \
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"fdt_addr=0x83000000\0" \
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"boot_name=boot.img\0" \
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"boot_addr=0x8007f800\0"
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#ifndef CONFIG_BOOTCOMMAND
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#define CONFIG_BOOTCOMMAND "if smhload ${boot_name} ${boot_addr}; then " \
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" set bootargs; " \
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" abootimg addr ${boot_addr}; " \
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" abootimg get dtb --index=0 fdt_addr; " \
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" bootm ${boot_addr} ${boot_addr} " \
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" ${fdt_addr}; " \
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"else; " \
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" set fdt_high 0xffffffffffffffff; " \
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" set initrd_high 0xffffffffffffffff; " \
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" smhload ${kernel_name} ${kernel_addr}; " \
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" smhload ${fdtfile} ${fdt_addr}; " \
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" smhload ${initrd_name} ${initrd_addr} "\
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" initrd_end; " \
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" fdt addr ${fdt_addr}; fdt resize; " \
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" fdt chosen ${initrd_addr} ${initrd_end}; " \
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" booti $kernel_addr - $fdt_addr; " \
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"fi"
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#endif
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#endif
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_MAXARGS 64 /* max command args */
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#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
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#define CONFIG_SYS_FLASH_BASE 0x08000000
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/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
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#define CONFIG_SYS_MAX_FLASH_SECT 259
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/* Store environment at top of flash in the same location as blank.img */
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/* in the Juno firmware. */
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#else
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#define CONFIG_SYS_FLASH_BASE 0x0C000000
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/* 256 x 256KiB sectors */
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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/* Store environment at top of flash */
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#endif
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#ifdef CONFIG_USB_EHCI_HCD
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
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#endif
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
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#define FLASH_MAX_SECTOR_SIZE 0x00040000
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#endif /* __VEXPRESS_AEMV8A_H */
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