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https://github.com/AsahiLinux/u-boot
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aa6e94deab
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
192 lines
5.4 KiB
C
192 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017-2020 NXP
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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* Layerscape PCIe driver
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*/
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#ifndef _PCIE_LAYERSCAPE_H_
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#define _PCIE_LAYERSCAPE_H_
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#include <pci.h>
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#include <linux/sizes.h>
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#include <asm/arch-fsl-layerscape/svr.h>
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#include <asm/arch-ls102xa/svr.h>
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#ifndef CFG_SYS_PCI_MEMORY_BUS
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#define CFG_SYS_PCI_MEMORY_BUS CFG_SYS_SDRAM_BASE
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#endif
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#ifndef CFG_SYS_PCI_MEMORY_PHYS
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#define CFG_SYS_PCI_MEMORY_PHYS CFG_SYS_SDRAM_BASE
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#endif
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#ifndef CFG_SYS_PCI_MEMORY_SIZE
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#define CFG_SYS_PCI_MEMORY_SIZE SZ_4G
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#endif
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#ifndef CFG_SYS_PCI_EP_MEMORY_BASE
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#define CFG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
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#endif
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#define PCIE_PHYS_SIZE 0x200000000
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#define LS2088A_PCIE_PHYS_SIZE 0x800000000
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#define LS2088A_PCIE1_PHYS_ADDR 0x2000000000
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/* iATU registers */
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#define PCIE_ATU_VIEWPORT 0x900
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#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
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#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
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#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
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#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
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#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
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#define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
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#define PCIE_ATU_REGION_NUM 6
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#define PCIE_ATU_REGION_NUM_SRIOV 24
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#define PCIE_ATU_CR1 0x904
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#define PCIE_ATU_TYPE_MEM (0x0 << 0)
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#define PCIE_ATU_TYPE_IO (0x2 << 0)
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#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
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#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
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#define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
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#define PCIE_ATU_CR2 0x908
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#define PCIE_ATU_ENABLE (0x1 << 31)
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#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
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#define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
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#define PCIE_ATU_VFBAR_MATCH_MODE_EN BIT(26)
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#define PCIE_ATU_BAR_NUM(bar) ((bar) << 8)
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#define PCIE_ATU_LOWER_BASE 0x90C
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#define PCIE_ATU_UPPER_BASE 0x910
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#define PCIE_ATU_LIMIT 0x914
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#define PCIE_ATU_LOWER_TARGET 0x918
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#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
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#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
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#define PCIE_ATU_UPPER_TARGET 0x91C
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/* DBI registers */
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#define PCIE_SRIOV 0x178
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#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
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#define PCIE_DBI_RO_WR_EN BIT(0)
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#define PCIE_MISC_CONTROL_1_OFF 0x8BC
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#define PCIE_LINK_CAP 0x7c
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#define PCIE_LINK_SPEED_MASK 0xf
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#define PCIE_LINK_WIDTH_MASK 0x3f0
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#define PCIE_LINK_STA 0x82
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#define LTSSM_STATE_MASK 0x3f
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#define LTSSM_PCIE_L0 0x11 /* L0 state */
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#define PCIE_DBI_SIZE 0x100000 /* 1M */
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#define PCIE_LCTRL0_CFG2_ENABLE (1 << 31)
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#define PCIE_LCTRL0_VF(vf) ((vf) << 22)
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#define PCIE_LCTRL0_PF(pf) ((pf) << 16)
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#define PCIE_LCTRL0_VF_ACTIVE (1 << 21)
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#define PCIE_LCTRL0_VAL(pf, vf) (PCIE_LCTRL0_PF(pf) | \
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PCIE_LCTRL0_VF(vf) | \
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((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \
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PCIE_LCTRL0_CFG2_ENABLE)
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#define PCIE_NO_SRIOV_BAR_BASE 0x1000
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#define FSL_PCIE_EP_MIN_APERTURE 4096 /* 4 Kbytes */
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#define PCIE_PF_NUM 2
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#define PCIE_VF_NUM 64
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#define BAR_NUM 8
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#define PCIE_BAR0_SIZE SZ_4K
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#define PCIE_BAR1_SIZE SZ_8K
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#define PCIE_BAR2_SIZE SZ_4K
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#define PCIE_BAR4_SIZE SZ_1M
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#define PCIE_SRIOV_VFBAR0 0x19C
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#define PCIE_MASK_OFFSET(flag, pf, off) ((flag) ? 0 : (0x1000 + (off) * (pf)))
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/* LUT registers */
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#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
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#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
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#define PCIE_LUT_ENABLE (1 << 31)
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#define PCIE_LUT_ENTRY_COUNT 32
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/* PF Controll registers */
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#define PCIE_PF_CONFIG 0x14
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#define PCIE_PF_VF_CTRL 0x7F8
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#define PCIE_PF_DBG 0x7FC
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#define PCIE_CONFIG_READY (1 << 0)
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#define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx))
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#define PCIE_SYS_BASE_ADDR 0x3400000
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#define PCIE_CCSR_SIZE 0x0100000
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/* CS2 */
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#define PCIE_CS2_OFFSET 0x1000 /* For PCIe without SR-IOV */
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/* LS1021a PCIE space */
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#define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL
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#define LS1021_PCIE_SPACE_SIZE 0x0800000000ULL
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/* LS1021a PEX1/2 Misc Ports Status Register */
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#define LS1021_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
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#define LS1021_LTSSM_STATE_SHIFT 20
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/* LX2160a PF1 offset */
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#define LX2160_PCIE_PF1_OFFSET 0x8000
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/* layerscape PF1 offset */
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#define LS_PCIE_PF1_OFFSET 0x20000
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struct ls_pcie {
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void __iomem *dbi;
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void __iomem *lut;
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void __iomem *ctrl;
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int idx;
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bool big_endian;
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int mode;
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};
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struct ls_pcie_rc {
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struct ls_pcie *pcie;
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struct list_head list;
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struct udevice *bus;
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struct fdt_resource dbi_res;
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struct fdt_resource lut_res;
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struct fdt_resource ctrl_res;
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struct fdt_resource cfg_res;
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void __iomem *cfg0;
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void __iomem *cfg1;
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bool enabled;
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int next_lut_index;
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int stream_id_cur;
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};
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struct ls_pcie_ep {
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struct fdt_resource addr_res;
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struct ls_pcie *pcie;
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struct udevice *bus;
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void __iomem *addr;
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u32 cfg2_flag;
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u32 sriov_flag;
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u32 pf1_offset;
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u32 num_ib_wins;
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u32 num_ob_wins;
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u8 max_functions;
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};
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extern struct list_head ls_pcie_list;
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unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset);
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void dbi_writel(struct ls_pcie *pcie, unsigned int value, unsigned int offset);
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unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset);
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void ctrl_writel(struct ls_pcie *pcie, unsigned int value, unsigned int offset);
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void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
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u64 phys, u64 bus_addr, u64 size);
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void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
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int type, int idx, int bar, u64 phys);
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void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type);
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int ls_pcie_link_up(struct ls_pcie *pcie);
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void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie);
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void ls_pcie_dbi_ro_wr_dis(struct ls_pcie *pcie);
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#endif /* _PCIE_LAYERSCAPE_H_ */
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