mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 18:41:03 +00:00
177178685a
By providing entries in the binman node of the device tree, binman will be able to find and package board config artifacts generated by TIBoardConfig with sysfw.bin and generate the final image sysfw.itb. It will also pick out the R5 SPL and sign it with the help of TI signing entry and generate the final tiboot3.bin. Entries for A72 build have been added to k3-j721e-binman.dtsi to generate tispl.bin and u-boot.img. Support has been added for both HS-SE(SR 1.1), HS-FS(SR 2.0) and GP images In HS-SE, the encrypted system firmware binary must be signed along with the signed certificate binary. HS-SE: * tiboot3-j721e_sr1_1-hs-evm.bin * sysfw-j721e_sr1_1-hs-evm.itb * tispl.bin * u-boot.img HS-FS: * tiboot3-j721e_sr2-hs-fs-evm.bin * sysfw-j721e_sr2-hs-fs-evm.itb * tispl.bin * u-boot.img GP: * tiboot3.bin -->tiboot3-j721e-gp-evm.bin * sysfw.itb --> sysfw-j721e-gp-evm.itb * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by J721E requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs sysfw.itb: * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass <sjg@chromium.org> [afd@ti.com: changed output binary names appropriately] Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
285 lines
4 KiB
Text
285 lines
4 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/net/ti-dp83867.h>
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#include "k3-j721e-binman.dtsi"
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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tick-timer = &timer1;
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};
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aliases {
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ethernet0 = &cpsw_port1;
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spi0 = &ospi0;
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remoteproc0 = &mcu_r5fss0_core0;
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remoteproc1 = &mcu_r5fss0_core1;
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remoteproc2 = &main_r5fss0_core0;
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remoteproc3 = &main_r5fss0_core1;
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remoteproc4 = &main_r5fss1_core0;
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remoteproc5 = &main_r5fss1_core1;
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remoteproc6 = &c66_0;
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remoteproc7 = &c66_1;
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remoteproc8 = &c71_0;
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i2c0 = &wkup_i2c0;
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i2c1 = &mcu_i2c0;
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i2c2 = &main_i2c0;
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mmc1 = &main_sdhci1; /* SD Card */
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};
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};
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&cbass_main{
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bootph-pre-ram;
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main_navss: bus@30000000 {
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bootph-pre-ram;
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};
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};
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&cbass_mcu_wakeup {
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bootph-pre-ram;
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timer1: timer@40400000 {
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compatible = "ti,omap5430-timer";
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reg = <0x0 0x40400000 0x0 0x80>;
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ti,timer-alwon;
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clock-frequency = <25000000>;
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bootph-pre-ram;
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};
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mcu_navss: bus@28380000 {
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bootph-pre-ram;
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ringacc@2b800000 {
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reg = <0x0 0x2b800000 0x0 0x400000>,
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<0x0 0x2b000000 0x0 0x400000>,
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<0x0 0x28590000 0x0 0x100>,
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<0x0 0x2a500000 0x0 0x40000>,
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<0x0 0x28440000 0x0 0x40000>;
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reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
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bootph-pre-ram;
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};
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dma-controller@285c0000 {
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reg = <0x0 0x285c0000 0x0 0x100>,
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<0x0 0x284c0000 0x0 0x4000>,
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<0x0 0x2a800000 0x0 0x40000>,
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<0x0 0x284a0000 0x0 0x4000>,
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<0x0 0x2aa00000 0x0 0x40000>,
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<0x0 0x28400000 0x0 0x2000>;
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reg-names = "gcfg", "rchan", "rchanrt", "tchan",
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"tchanrt", "rflow";
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bootph-pre-ram;
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};
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};
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chipid@43000014 {
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bootph-pre-ram;
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};
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};
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&secure_proxy_main {
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bootph-pre-ram;
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};
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&dmsc {
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bootph-pre-ram;
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k3_sysreset: sysreset-controller {
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compatible = "ti,sci-sysreset";
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bootph-pre-ram;
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};
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};
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&k3_pds {
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bootph-pre-ram;
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};
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&k3_clks {
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bootph-pre-ram;
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};
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&k3_reset {
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bootph-pre-ram;
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};
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&wkup_pmx0 {
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bootph-pre-ram;
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};
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&main_pmx0 {
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bootph-pre-ram;
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};
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&main_uart0 {
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bootph-pre-ram;
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};
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&mcu_uart0 {
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bootph-pre-ram;
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};
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&main_sdhci0 {
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status = "disabled";
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};
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&main_sdhci1 {
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bootph-pre-ram;
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};
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&wiz3_pll1_refclk {
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assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
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assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
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};
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&main_usbss0_pins_default {
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bootph-pre-ram;
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};
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&usbss0 {
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bootph-pre-ram;
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};
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&usb0 {
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dr_mode = "host";
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bootph-pre-ram;
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};
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&wiz2_pll1_refclk {
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assigned-clocks = <&wiz2_pll1_refclk>, <&wiz2_pll0_refclk>;
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assigned-clock-parents = <&k3_clks 294 0>, <&k3_clks 294 11>;
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};
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&main_usbss1_pins_default {
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bootph-pre-ram;
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};
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&usbss1 {
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bootph-pre-ram;
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};
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&usb1 {
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dr_mode = "host";
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bootph-pre-ram;
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};
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&mcu_cpsw {
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reg = <0x0 0x46000000 0x0 0x200000>,
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<0x0 0x40f00200 0x0 0x2>;
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reg-names = "cpsw_nuss", "mac_efuse";
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/delete-property/ ranges;
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cpsw-phy-sel@40f04040 {
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compatible = "ti,am654-cpsw-phy-sel";
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reg= <0x0 0x40f04040 0x0 0x4>;
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reg-names = "gmii-sel";
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};
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};
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&main_mmc1_pins_default {
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bootph-pre-ram;
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};
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&wkup_i2c0_pins_default {
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bootph-pre-ram;
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};
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&wkup_i2c0 {
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bootph-pre-ram;
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};
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&mcu_i2c0 {
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bootph-pre-ram;
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};
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&mcu_i2c1 {
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status = "disabled";
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};
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&main_i2c0 {
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status = "disabled";
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};
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&main_i2c1 {
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status = "disabled";
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};
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&main_i2c2 {
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status = "disabled";
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};
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&main_i2c3 {
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status = "disabled";
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};
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&main_i2c4 {
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status = "disabled";
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};
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&main_i2c5 {
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status = "disabled";
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};
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&main_i2c6 {
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status = "disabled";
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};
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&mcu_i2c0_pins_default {
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bootph-pre-ram;
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};
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&mcu_fss0_ospi0_pins_default {
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bootph-pre-ram;
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};
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&fss {
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bootph-pre-ram;
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};
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&hbmc {
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status = "disabled";
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};
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&ospi0 {
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bootph-pre-ram;
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flash@0 {
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bootph-pre-ram;
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partition@3fc0000 {
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label = "ospi.phypattern";
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reg = <0x3fc0000 0x40000>;
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bootph-pre-ram;
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};
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};
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};
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&serdes_ln_ctrl {
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u-boot,mux-autoprobe;
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};
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&usb_serdes_mux {
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u-boot,mux-autoprobe;
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};
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&pcie0_rc {
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status = "disabled";
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};
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&pcie1_rc {
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status = "disabled";
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};
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&pcie0_ep {
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status = "disabled";
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};
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&pcie1_ep {
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status = "disabled";
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};
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&dss {
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status = "disabled";
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};
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