Fabio Estevam 8f2e2f15ff mx6: clock: Fix the logic for reading axi_alt_sel ... According to the IMX6DQRM Reference Manual, the description of bit 7 (axi_alt_sel) of the CCM_CBCDR register is: "AXI alternative clock select 0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock 1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock " The current logic is inverted, so fix it to match the reference manual. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>		2016-07-20 18:26:37 +02:00
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clock.c	mx6: clock: Fix the logic for reading axi_alt_sel	2016-07-20 18:26:37 +02:00
ddr.c	imx: mx6: ddr: support i.MX6D/QPlus	2016-05-24 14:59:56 +02:00
Kconfig	mx6: Add Phytec PCM058 i.MX6 Quad	2016-07-12 17:58:48 +02:00
Makefile	imx: hab: rework secure boot support for imx6	2015-10-30 15:20:57 +01:00
mp.c	mx6: add support of multi-processor command	2014-08-20 11:52:54 +02:00
soc.c	imx: mx6: correct get_cpu_speed_grade_hz for i.MX6DQP	2016-05-24 14:59:56 +02:00