mirror of
https://github.com/AsahiLinux/u-boot
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6b59304602
Make sure to reset the switch core at probe time. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
305 lines
8.1 KiB
Text
305 lines
8.1 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mscc,jr2";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mips,mips24KEc";
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device_type = "cpu";
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clocks = <&cpu_clk>;
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reg = <0>;
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};
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};
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aliases {
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serial0 = &uart0;
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};
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cpuintc: interrupt-controller@0 {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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cpu_clk: cpu-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <500000000>;
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};
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ahb_clk: ahb-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <250000000>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x70000000 0x2000000>;
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interrupt-parent = <&intc>;
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cpu_ctrl: syscon@0 {
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compatible = "mscc,jr2-cpu-syscon", "syscon";
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reg = <0x0 0x2c>;
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};
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intc: interrupt-controller@70 {
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compatible = "mscc,jr2-icpu-intr";
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reg = <0x70 0x94>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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uart0: serial@100000 {
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pinctrl-0 = <&uart_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x100000 0x20>;
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interrupts = <6>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart2: serial@100800 {
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pinctrl-0 = <&uart2_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x100800 0x20>;
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interrupts = <7>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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spi0: spi-master@101000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mscc,jaguar2-spi", "snps,dw-apb-ssi";
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reg = <0x101000 0x40>;
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num-chipselect = <4>;
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bus-num = <0>;
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reg-io-width = <4>;
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reg-shift = <2>;
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spi-max-frequency = <18000000>; /* input clock */
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clocks = <&ahb_clk>;
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status = "disabled";
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};
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reset@1010008 {
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compatible = "mscc,jr2-chip-reset";
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reg = <0x1010008 0x4>;
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};
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gpio: pinctrl@1070034 {
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compatible = "mscc,jaguar2-pinctrl";
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reg = <0x1010038 0x90>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio 0 0 64>;
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sgpio_pins: sgpio-pins {
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pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
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function = "sg0";
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};
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sgpio1_pins: sgpio1-pins {
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pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13";
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function = "sg1";
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};
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sgpio2_pins: sgpio2-pins {
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pins = "GPIO_30", "GPIO_31",
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"GPIO_32", "GPIO_33";
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function = "sg2";
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};
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uart_pins: uart-pins {
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pins = "GPIO_10", "GPIO_11";
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function = "uart";
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};
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uart2_pins: uart2-pins {
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pins = "GPIO_24", "GPIO_25";
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function = "uart2";
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};
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};
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sgpio: gpio@1010150 {
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compatible = "mscc,ocelot-sgpio";
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status = "disabled";
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pinctrl-0 = <&sgpio_pins>;
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pinctrl-names = "default";
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reg = <0x1010150 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&sgpio 0 0 64>;
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gpio-bank-name = "sgpio0_";
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sgpio-clock = <0x14>;
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};
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sgpio1: gpio@101025c {
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compatible = "mscc,ocelot-sgpio";
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status = "disabled";
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pinctrl-0 = <&sgpio1_pins>;
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pinctrl-names = "default";
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reg = <0x101025c 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&sgpio1 0 0 64>;
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gpio-bank-name = "sgpio1_";
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sgpio-clock = <0x14>;
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};
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sgpio2: gpio@1010368 {
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compatible = "mscc,ocelot-sgpio";
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status = "disabled";
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pinctrl-0 = <&sgpio2_pins>;
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pinctrl-names = "default";
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reg = <0x1010368 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&sgpio2 0 0 64>;
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gpio-bank-name = "sgpio2_";
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sgpio-clock = <0x14>;
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};
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switch: switch@1010000 {
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compatible = "mscc,vsc7454-switch";
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reg = <0x01040000 0x0100>, // VTSS_TO_DEV_0
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<0x01050000 0x0100>, // VTSS_TO_DEV_1
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<0x01060000 0x0100>, // VTSS_TO_DEV_2
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<0x01070000 0x0100>, // VTSS_TO_DEV_3
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<0x01080000 0x0100>, // VTSS_TO_DEV_4
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<0x01090000 0x0100>, // VTSS_TO_DEV_5
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<0x010a0000 0x0100>, // VTSS_TO_DEV_6
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<0x010b0000 0x0100>, // VTSS_TO_DEV_7
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<0x010c0000 0x0100>, // VTSS_TO_DEV_8
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<0x010d0000 0x0100>, // VTSS_TO_DEV_9
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<0x010e0000 0x0100>, // VTSS_TO_DEV_10
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<0x010f0000 0x0100>, // VTSS_TO_DEV_11
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<0x01100000 0x0100>, // VTSS_TO_DEV_12
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<0x01110000 0x0100>, // VTSS_TO_DEV_13
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<0x01120000 0x0100>, // VTSS_TO_DEV_14
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<0x01130000 0x0100>, // VTSS_TO_DEV_15
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<0x01140000 0x0100>, // VTSS_TO_DEV_16
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<0x01150000 0x0100>, // VTSS_TO_DEV_17
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<0x01160000 0x0100>, // VTSS_TO_DEV_18
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<0x01170000 0x0100>, // VTSS_TO_DEV_19
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<0x01180000 0x0100>, // VTSS_TO_DEV_20
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<0x01190000 0x0100>, // VTSS_TO_DEV_21
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<0x011a0000 0x0100>, // VTSS_TO_DEV_22
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<0x011b0000 0x0100>, // VTSS_TO_DEV_23
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<0x011c0000 0x0100>, // VTSS_TO_DEV_24
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<0x011d0000 0x0100>, // VTSS_TO_DEV_25
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<0x011e0000 0x0100>, // VTSS_TO_DEV_26
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<0x011f0000 0x0100>, // VTSS_TO_DEV_27
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<0x01200000 0x0100>, // VTSS_TO_DEV_28
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<0x01210000 0x0100>, // VTSS_TO_DEV_29
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<0x01220000 0x0100>, // VTSS_TO_DEV_30
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<0x01230000 0x0100>, // VTSS_TO_DEV_31
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<0x01240000 0x0100>, // VTSS_TO_DEV_32
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<0x01250000 0x0100>, // VTSS_TO_DEV_33
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<0x01260000 0x0100>, // VTSS_TO_DEV_34
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<0x01270000 0x0100>, // VTSS_TO_DEV_35
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<0x01280000 0x0100>, // VTSS_TO_DEV_36
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<0x01290000 0x0100>, // VTSS_TO_DEV_37
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<0x012a0000 0x0100>, // VTSS_TO_DEV_38
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<0x012b0000 0x0100>, // VTSS_TO_DEV_39
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<0x012c0000 0x0100>, // VTSS_TO_DEV_40
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<0x012d0000 0x0100>, // VTSS_TO_DEV_41
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<0x012e0000 0x0100>, // VTSS_TO_DEV_42
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<0x012f0000 0x0100>, // VTSS_TO_DEV_43
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<0x01300000 0x0100>, // VTSS_TO_DEV_44
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<0x01310000 0x0100>, // VTSS_TO_DEV_45
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<0x01320000 0x0100>, // VTSS_TO_DEV_46
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<0x01330000 0x0100>, // VTSS_TO_DEV_47
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<0x01f00000 0x100000>, // ANA_AC
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<0x01d00000 0x100000>, // ANA_CL
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<0x01e00000 0x100000>, // ANA_L2
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<0x01410000 0x10000>, // ASM
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<0x01460000 0x10000>, // HSIO
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<0x01420000 0x00000>, // LRN
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<0x017d0000 0x10000>, // QFWD
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<0x01020000 0x20000>, // QS
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<0x017e0000 0x10000>, // QSYS
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<0x01b00000 0x80000>, // REW
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<0x01010000 0x100>, // GCB
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<0x00000000 0x100>; // ICPU
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reg-names = "port0", "port1", "port2", "port3", "port4",
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"port5", "port6", "port7", "port8", "port9",
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"port10", "port11", "port12", "port13",
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"port14", "port15", "port16", "port17",
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"port18", "port19", "port20", "port21",
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"port22", "port23", "port24", "port25",
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"port26", "port27", "port28", "port29",
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"port30", "port31", "port32", "port33",
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"port34", "port35", "port36", "port37",
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"port38", "port39", "port40", "port41",
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"port42", "port43", "port44", "port45",
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"port46", "port47", "ana_ac", "ana_cl",
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"ana_l2", "asm", "hsio", "lrn", "qfwd",
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"qs", "qsys", "rew", "gcb", "icpu";
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status = "okay";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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mdio0: mdio@010100c8 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mscc,jr2-miim";
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reg = <0x010100c8 0x24>;
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status = "disabled";
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};
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mdio1: mdio@010100ec {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mscc,jr2-miim";
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reg = <0x010100ec 0x24>;
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status = "disabled";
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};
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mdio2: mdio@01010110 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mscc,jr2-miim";
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reg = <0x01010110 0x24>;
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status = "disabled";
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};
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hsio: syscon@10d0000 {
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compatible = "mscc,jr2-hsio", "syscon", "simple-mfd";
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reg = <0x10d0000 0x10000>;
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serdes_hsio: serdes_hsio {
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compatible = "mscc,vsc7454-serdes";
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#phy-cells = <3>;
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};
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};
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};
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};
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