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02bb1fa09e
This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
32 lines
882 B
C
32 lines
882 B
C
/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DT_BINDINGS_RESET_BCM63268_H
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#define __DT_BINDINGS_RESET_BCM63268_H
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#define BCM63268_RST_SPI 0
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#define BCM63268_RST_IPSEC 1
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#define BCM63268_RST_EPHY 2
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#define BCM63268_RST_SAR 3
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#define BCM63268_RST_ENETSW 4
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#define BCM63268_RST_USBS 5
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#define BCM63268_RST_USBH 6
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#define BCM63268_RST_PCM 7
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#define BCM63268_RST_PCIE_CORE 8
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#define BCM63268_RST_PCIE 9
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#define BCM63268_RST_PCIE_EXT 10
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#define BCM63268_RST_WLAN_SHIM 11
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#define BCM63268_RST_DDR_PHY 12
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#define BCM63268_RST_FAP0 13
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#define BCM63268_RST_WLAN_UBUS 14
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#define BCM63268_RST_DECT 15
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#define BCM63268_RST_FAP1 16
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#define BCM63268_RST_PCIE_HARD 17
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#define BCM63268_RST_GPHY 18
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#endif /* __DT_BINDINGS_RESET_BCM63268_H */
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