mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 01:38:22 +00:00
10117a2985
Drop CONFIG_SYS_MEMORY_TOP. Rename CONFIG_SYS_TEXT_ADDR to XTENSA_SYS_TEXT_ADDR. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
116 lines
4.1 KiB
Text
116 lines
4.1 KiB
Text
/*
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* (C) Copyright 2008 - 2013 Tensilica, Inc.
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* (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <asm/ldscript.h>
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#include <asm/arch/core.h>
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#include <asm/addrspace.h>
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#include <asm-offsets.h>
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OUTPUT_ARCH(xtensa)
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ENTRY(_start)
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/*
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* U-Boot resets from SYSROM and unpacks itself from a ROM store to RAM.
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* The reset vector is usually near the base of SYSROM and has room
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* above it for the ROM store into which the rest of U-Boot is packed.
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* The ROM store also needs to be above any other vectors that are in ROM.
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* If a core has its vectors near the top of ROM, this must be edited.
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*
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* Note that to run C code out of ROM, the processor would have to support
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* 'relocatable' exception vectors and provide a scratch memory for the
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* initial stack. Not all Xtensa processor configurations support that, so
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* we can simplify the boot process and unpack U-Boot to RAM immediately.
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* This, however, requires that memory have been initialized throug some
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* other means (serial ROM, for example) or are initialized early (requiring
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* an assembler function. See start.S for more details)
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*/
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SECTIONS
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{
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. = + SIZEOF_HEADERS;
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SECTION_ResetVector(XCHAL_RESET_VECTOR_VADDR, LMA_EQ_VMA)
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.reloc_table ALIGN(4) : FOLLOWING(.ResetVector.text)
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{
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__reloc_table_start = ABSOLUTE(.);
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#if XCHAL_HAVE_WINDOWED
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RELOCATE2(WindowVectors,text);
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#endif
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RELOCATE2(KernelExceptionVector,literal);
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RELOCATE2(KernelExceptionVector,text);
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RELOCATE2(UserExceptionVector,literal);
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RELOCATE2(UserExceptionVector,text);
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RELOCATE2(DoubleExceptionVector,literal);
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RELOCATE2(DoubleExceptionVector,text);
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RELOCATE1(text);
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RELOCATE1(rodata);
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RELOCATE1(data);
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RELOCATE1(u_boot_list);
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__reloc_table_end = ABSOLUTE(.);
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}
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#if XCHAL_HAVE_WINDOWED
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SECTION_VECTOR(WindowVectors,text,XCHAL_WINDOW_VECTORS_VADDR,
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FOLLOWING(.reloc_table))
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SECTION_VECTOR(KernelExceptionVector,literal,XCHAL_KERNEL_VECTOR_VADDR-8,
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FOLLOWING(.WindowVectors.text))
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#else
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SECTION_VECTOR(KernelExceptionVector,literal,XCHAL_KERNEL_VECTOR_VADDR-8,
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FOLLOWING(.reloc_table))
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#endif
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SECTION_VECTOR(KernelExceptionVector,text,XCHAL_KERNEL_VECTOR_VADDR,
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FOLLOWING(.KernelExceptionVector.literal))
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SECTION_VECTOR(UserExceptionVector,literal,XCHAL_USER_VECTOR_VADDR-8,
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FOLLOWING(.KernelExceptionVector.text))
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SECTION_VECTOR(UserExceptionVector,text,XCHAL_USER_VECTOR_VADDR,
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FOLLOWING(.UserExceptionVector.literal))
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SECTION_VECTOR(DoubleExceptionVector,literal,XCHAL_DOUBLEEXC_VECTOR_VADDR-8,
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FOLLOWING(.UserExceptionVector.text))
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SECTION_VECTOR(DoubleExceptionVector,text,XCHAL_DOUBLEEXC_VECTOR_VADDR,
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FOLLOWING(.DoubleExceptionVector.literal))
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__monitor_start = XTENSA_SYS_TEXT_ADDR;
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SECTION_text(XTENSA_SYS_TEXT_ADDR, FOLLOWING(.DoubleExceptionVector.text))
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SECTION_rodata(ALIGN(16), FOLLOWING(.text))
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SECTION_u_boot_list(ALIGN(16), FOLLOWING(.rodata))
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SECTION_data(ALIGN(16), FOLLOWING(.u_boot_list))
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__reloc_end = .;
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__init_end = .;
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SECTION_bss(__init_end (OVERLAY),)
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__monitor_end = .;
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/*
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* On many Xtensa boards a region of RAM may be mapped to the ROM address
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* space to facilitate on-chip-debug, and U-Boot must fit with that region.
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* The config variables CONFIG_SYS_MONITOR_* define the region.
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* If U-Boot extends beyond this region it will appear discontiguous in the
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* address space and is in danger of overwriting itself during unpacking
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* ("relocation").
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* This causes U-Boot to crash in a way that is difficult to debug. On some
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* boards (such as xtav60) the region is small enough that U-Boot will not
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* fit if compiled entirely with -O0 (a common scenario). To avoid a lengthy
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* debugging session when this happens, ensure a link-time error occurs.
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*
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*/
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ASSERT(__monitor_end - __monitor_start <= CONFIG_SYS_MONITOR_LEN,
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"U-Boot ROM image is too large. Check optimization level.")
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SECTION_xtensa
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SECTION_debug
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/DISCARD/ : { *(.dynstr*) }
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/DISCARD/ : { *(.hash*) }
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/DISCARD/ : { *(.interp) }
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/DISCARD/ : { *(.got*) }
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/DISCARD/ : { *(.dynsym) }
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}
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