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295326231d
For Electro-Magnetic Compatibility. Set CPLL, SPLL2, MPLL, VPPLL, GPPLL, DPLL* to SSC rate 1 percent. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
41 lines
1.2 KiB
C
41 lines
1.2 KiB
C
/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include "../init.h"
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#include "../sc64-regs.h"
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#include "pll.h"
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int uniphier_ld20_pll_init(const struct uniphier_board_data *bd)
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{
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uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
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/* do nothing for SPLL */
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uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
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uniphier_ld20_sscpll_init(SC_MPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
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uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
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uniphier_ld20_sscpll_init(SC_GPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
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mdelay(1);
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uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
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uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL);
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uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL);
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uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL);
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uniphier_ld20_sscpll_ssc_en(SC_GPPLLCTRL);
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uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
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uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
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uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
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uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
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uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
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uniphier_ld20_dspll_init(SC_VPLL8KCTRL);
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uniphier_ld20_dspll_init(SC_A2PLLCTRL);
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return 0;
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}
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