mirror of
https://github.com/AsahiLinux/u-boot
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258 lines
9.3 KiB
C
258 lines
9.3 KiB
C
/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_MX31_REGS_H
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#define __ASM_ARCH_MX31_REGS_H
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#define __REG(x) (*((volatile u32 *)(x)))
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#define __REG16(x) (*((volatile u16 *)(x)))
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#define __REG8(x) (*((volatile u8 *)(x)))
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#define CCM_BASE 0x53f80000
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#define CCM_CCMR (CCM_BASE + 0x00)
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#define CCM_PDR0 (CCM_BASE + 0x04)
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#define CCM_PDR1 (CCM_BASE + 0x08)
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#define CCM_RCSR (CCM_BASE + 0x0c)
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#define CCM_MPCTL (CCM_BASE + 0x10)
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#define CCM_UPCTL (CCM_BASE + 0x14)
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#define CCM_SPCTL (CCM_BASE + 0x18)
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#define CCM_COSR (CCM_BASE + 0x1C)
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#define CCM_CGR0 (CCM_BASE + 0x20)
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#define CCM_CGR1 (CCM_BASE + 0x24)
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#define CCM_CGR2 (CCM_BASE + 0x28)
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#define CCMR_MDS (1 << 7)
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#define CCMR_SBYCS (1 << 4)
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#define CCMR_MPE (1 << 3)
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#define CCMR_PRCS_MASK (3 << 1)
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#define CCMR_FPM (1 << 1)
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#define CCMR_CKIH (2 << 1)
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#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
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#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
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#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
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#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
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#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
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#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
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#define PDR0_MCU_PODF(x) ((x) & 0x7)
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#define PLL_PD(x) (((x) & 0xf) << 26)
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#define PLL_MFD(x) (((x) & 0x3ff) << 16)
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#define PLL_MFI(x) (((x) & 0xf) << 10)
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#define PLL_MFN(x) (((x) & 0x3ff) << 0)
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#define WEIM_ESDCTL0 0xB8001000
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#define WEIM_ESDCFG0 0xB8001004
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#define WEIM_ESDCTL1 0xB8001008
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#define WEIM_ESDCFG1 0xB800100C
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#define WEIM_ESDMISC 0xB8001010
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#define ESDCTL_SDE (1 << 31)
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#define ESDCTL_CMD_RW (0 << 28)
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#define ESDCTL_CMD_PRECHARGE (1 << 28)
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#define ESDCTL_CMD_AUTOREFRESH (2 << 28)
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#define ESDCTL_CMD_LOADMODEREG (3 << 28)
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#define ESDCTL_CMD_MANUALREFRESH (4 << 28)
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#define ESDCTL_ROW_13 (2 << 24)
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#define ESDCTL_ROW(x) ((x) << 24)
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#define ESDCTL_COL_9 (1 << 20)
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#define ESDCTL_COL(x) ((x) << 20)
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#define ESDCTL_DSIZ(x) ((x) << 16)
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#define ESDCTL_SREFR(x) ((x) << 13)
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#define ESDCTL_PWDT(x) ((x) << 10)
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#define ESDCTL_FP(x) ((x) << 8)
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#define ESDCTL_BL(x) ((x) << 7)
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#define ESDCTL_PRCT(x) ((x) << 0)
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#define WEIM_BASE 0xb8002000
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#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
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#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
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#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
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#define IOMUXC_BASE 0x43FAC000
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#define IOMUXC_GPR (IOMUXC_BASE + 0x8)
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#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
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#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
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#define IPU_BASE 0x53fc0000
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#define IPU_CONF IPU_BASE
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#define IPU_CONF_PXL_ENDIAN (1<<8)
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#define IPU_CONF_DU_EN (1<<7)
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#define IPU_CONF_DI_EN (1<<6)
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#define IPU_CONF_ADC_EN (1<<5)
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#define IPU_CONF_SDC_EN (1<<4)
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#define IPU_CONF_PF_EN (1<<3)
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#define IPU_CONF_ROT_EN (1<<2)
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#define IPU_CONF_IC_EN (1<<1)
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#define IPU_CONF_SCI_EN (1<<0)
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#define ARM_PPMRR 0x40000015
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#define WDOG_BASE 0x53FDC000
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/*
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* GPIO
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*/
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#define GPIO1_BASE 0x53FCC000
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#define GPIO2_BASE 0x53FD0000
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#define GPIO3_BASE 0x53FA4000
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#define GPIO_DR 0x00000000 /* data register */
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#define GPIO_GDIR 0x00000004 /* direction register */
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#define GPIO_PSR 0x00000008 /* pad status register */
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/*
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* Signal Multiplexing (IOMUX)
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*/
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/* bits in the SW_MUX_CTL registers */
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#define MUX_CTL_OUT_GPIO_DR (0 << 4)
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#define MUX_CTL_OUT_FUNC (1 << 4)
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#define MUX_CTL_OUT_ALT1 (2 << 4)
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#define MUX_CTL_OUT_ALT2 (3 << 4)
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#define MUX_CTL_OUT_ALT3 (4 << 4)
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#define MUX_CTL_OUT_ALT4 (5 << 4)
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#define MUX_CTL_OUT_ALT5 (6 << 4)
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#define MUX_CTL_OUT_ALT6 (7 << 4)
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#define MUX_CTL_IN_NONE (0 << 0)
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#define MUX_CTL_IN_GPIO (1 << 0)
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#define MUX_CTL_IN_FUNC (2 << 0)
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#define MUX_CTL_IN_ALT1 (4 << 0)
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#define MUX_CTL_IN_ALT2 (8 << 0)
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#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
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#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
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#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
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#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
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/* Register offsets based on IOMUXC_BASE */
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/* 0x00 .. 0x7b */
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#define MUX_CTL_RTS1 0x7c
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#define MUX_CTL_CTS1 0x7d
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#define MUX_CTL_DTR_DCE1 0x7e
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#define MUX_CTL_DSR_DCE1 0x7f
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#define MUX_CTL_CSPI2_SCLK 0x80
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#define MUX_CTL_CSPI2_SPI_RDY 0x81
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#define MUX_CTL_RXD1 0x82
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#define MUX_CTL_TXD1 0x83
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#define MUX_CTL_CSPI2_MISO 0x84
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#define MUX_CTL_CSPI2_SS0 0x85
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#define MUX_CTL_CSPI2_SS1 0x86
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#define MUX_CTL_CSPI2_SS2 0x87
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#define MUX_CTL_CSPI1_SS2 0x88
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#define MUX_CTL_CSPI1_SCLK 0x89
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#define MUX_CTL_CSPI1_SPI_RDY 0x8a
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#define MUX_CTL_CSPI2_MOSI 0x8b
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#define MUX_CTL_CSPI1_MOSI 0x8c
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#define MUX_CTL_CSPI1_MISO 0x8d
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#define MUX_CTL_CSPI1_SS0 0x8e
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#define MUX_CTL_CSPI1_SS1 0x8f
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/*
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* Helper macros for the MUX_[contact name]__[pin function] macros
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*/
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#define IOMUX_MODE_POS 9
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#define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact))
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/*
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* These macros can be used in mx31_gpio_mux() and have the form
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* MUX_[contact name]__[pin function]
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*/
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#define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC)
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#define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC)
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#define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
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#define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
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#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
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#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
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#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
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#define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC)
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#define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC)
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#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \
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IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
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#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
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#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
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#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
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#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
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#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
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#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
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#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
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IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
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#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
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#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
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#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
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/* PAD control registers for SDR/DDR */
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#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C)
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#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270)
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#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274)
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#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278)
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#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C)
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#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280)
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#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284)
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#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288)
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#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C)
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#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290)
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#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294)
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#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298)
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#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C)
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#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0)
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#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4)
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#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8)
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#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC)
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#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0)
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#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4)
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#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8)
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#define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC)
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#define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0)
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#define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4)
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#define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8)
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#define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC)
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#define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0)
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#define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4)
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#define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8)
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#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC)
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/*
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* Memory regions and CS
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*/
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#define IPU_MEM_BASE 0x70000000
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#define CSD0_BASE 0x80000000
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#define CSD1_BASE 0x90000000
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#define CS0_BASE 0xA0000000
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#define CS1_BASE 0xA8000000
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#define CS2_BASE 0xB0000000
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#define CS3_BASE 0xB2000000
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#define CS4_BASE 0xB4000000
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#define CS4_PSRAM_BASE 0xB5000000
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#define CS5_BASE 0xB6000000
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#define PCMCIA_MEM_BASE 0xC0000000
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/*
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* NAND controller
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*/
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#define NFC_BASE_ADDR 0xB8000000
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#endif /* __ASM_ARCH_MX31_REGS_H */
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