Leo Yu-Chi Liang f4512618ca riscv: ae350: Fix XIP config boot failure ... The booting flow is SPL -> OpenSBI -> U-Boot. The boot hart may change after OpenSBI and may not always be hart0, so wrap the related branch instruction with M-MODE. Current DTB setup for XIP is not valid. There is no chance for CONFIG_SYS_FDT_BASE, the DTB address used in XIP mode, to be returned. Fix this. Fixes: 2e8d2f8843 ("riscv: Remove OF_PRIOR_STAGE from RISC-V boards") Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>		2022-08-11 18:46:07 +08:00
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ax25-ae350	riscv: ae350: Fix XIP config boot failure	2022-08-11 18:46:07 +08:00