mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-15 09:27:35 +00:00
cbd7790a69
J721e SoM as a 64MB HyperFlash on board. Add pinmux and DT node for the same. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
367 lines
9.1 KiB
Text
367 lines
9.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "k3-j721e.dtsi"
|
|
|
|
/ {
|
|
memory@80000000 {
|
|
device_type = "memory";
|
|
/* 4G RAM */
|
|
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
|
|
<0x00000008 0x80000000 0x00000000 0x80000000>;
|
|
};
|
|
|
|
reserved_memory: reserved-memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
secure_ddr: optee@9e800000 {
|
|
reg = <0x00 0x9e800000 0x00 0x01800000>;
|
|
alignment = <0x1000>;
|
|
no-map;
|
|
};
|
|
|
|
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xa0000000 0x00 0x100000>;
|
|
no-map;
|
|
};
|
|
|
|
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
|
no-map;
|
|
};
|
|
|
|
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xa1000000 0x00 0x100000>;
|
|
no-map;
|
|
};
|
|
|
|
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
|
no-map;
|
|
};
|
|
|
|
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xa2000000 0x00 0x100000>;
|
|
no-map;
|
|
};
|
|
|
|
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
|
no-map;
|
|
};
|
|
|
|
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xa3000000 0x00 0x100000>;
|
|
no-map;
|
|
};
|
|
|
|
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
|
no-map;
|
|
};
|
|
|
|
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xa4000000 0x00 0x100000>;
|
|
no-map;
|
|
};
|
|
|
|
main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
|
no-map;
|
|
};
|
|
|
|
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xa5000000 0x00 0x100000>;
|
|
no-map;
|
|
};
|
|
|
|
main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xa5100000 0x00 0xf00000>;
|
|
no-map;
|
|
};
|
|
|
|
c66_1_dma_memory_region: c66-dma-memory@a6000000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xa6000000 0x00 0x100000>;
|
|
no-map;
|
|
};
|
|
|
|
c66_0_memory_region: c66-memory@a6100000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xa6100000 0x00 0xf00000>;
|
|
no-map;
|
|
};
|
|
|
|
c66_0_dma_memory_region: c66-dma-memory@a7000000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xa7000000 0x00 0x100000>;
|
|
no-map;
|
|
};
|
|
|
|
c66_1_memory_region: c66-memory@a7100000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xa7100000 0x00 0xf00000>;
|
|
no-map;
|
|
};
|
|
|
|
c71_0_dma_memory_region: c71-dma-memory@a8000000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xa8000000 0x00 0x100000>;
|
|
no-map;
|
|
};
|
|
|
|
c71_0_memory_region: c71-memory@a8100000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xa8100000 0x00 0xf00000>;
|
|
no-map;
|
|
};
|
|
|
|
rtos_ipc_memory_region: ipc-memories@aa000000 {
|
|
reg = <0x00 0xaa000000 0x00 0x01c00000>;
|
|
alignment = <0x1000>;
|
|
no-map;
|
|
};
|
|
};
|
|
};
|
|
|
|
&wkup_pmx0 {
|
|
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
|
|
pinctrl-single,pins = <
|
|
J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
|
|
J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
|
|
>;
|
|
};
|
|
|
|
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
|
|
pinctrl-single,pins = <
|
|
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
|
|
J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
|
|
J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
|
|
J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
|
|
J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
|
|
J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
|
|
J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
|
|
J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
|
|
J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
|
|
J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
|
|
J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
|
|
J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
|
|
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
|
|
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
|
|
>;
|
|
};
|
|
|
|
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
|
|
pinctrl-single,pins = <
|
|
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
|
|
J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
|
|
J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
|
|
J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
|
|
J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
|
|
J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
|
|
J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
|
|
J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
|
|
J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
|
|
J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
|
|
J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
|
|
>;
|
|
};
|
|
};
|
|
|
|
&hbmc {
|
|
status = "disabled";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
|
|
ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */
|
|
<0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */
|
|
|
|
flash@0,0 {
|
|
compatible = "cypress,hyperflash", "cfi-flash";
|
|
reg = <0x0 0x0 0x4000000>;
|
|
};
|
|
};
|
|
|
|
&ospi0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
|
|
|
|
flash@0{
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0x0>;
|
|
spi-tx-bus-width = <8>;
|
|
spi-rx-bus-width = <8>;
|
|
spi-max-frequency = <25000000>;
|
|
cdns,tshsl-ns = <60>;
|
|
cdns,tsd2d-ns = <60>;
|
|
cdns,tchsh-ns = <60>;
|
|
cdns,tslch-ns = <60>;
|
|
cdns,read-delay = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
};
|
|
};
|
|
|
|
&mailbox0_cluster0 {
|
|
interrupts = <436>;
|
|
|
|
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
|
ti,mbox-rx = <0 0 0>;
|
|
ti,mbox-tx = <1 0 0>;
|
|
};
|
|
|
|
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
|
ti,mbox-rx = <2 0 0>;
|
|
ti,mbox-tx = <3 0 0>;
|
|
};
|
|
};
|
|
|
|
&mailbox0_cluster1 {
|
|
interrupts = <432>;
|
|
|
|
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
|
ti,mbox-rx = <0 0 0>;
|
|
ti,mbox-tx = <1 0 0>;
|
|
};
|
|
|
|
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
|
ti,mbox-rx = <2 0 0>;
|
|
ti,mbox-tx = <3 0 0>;
|
|
};
|
|
};
|
|
|
|
&mailbox0_cluster2 {
|
|
interrupts = <428>;
|
|
|
|
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
|
ti,mbox-rx = <0 0 0>;
|
|
ti,mbox-tx = <1 0 0>;
|
|
};
|
|
|
|
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
|
ti,mbox-rx = <2 0 0>;
|
|
ti,mbox-tx = <3 0 0>;
|
|
};
|
|
};
|
|
|
|
&mailbox0_cluster3 {
|
|
interrupts = <424>;
|
|
|
|
mbox_c66_0: mbox-c66-0 {
|
|
ti,mbox-rx = <0 0 0>;
|
|
ti,mbox-tx = <1 0 0>;
|
|
};
|
|
|
|
mbox_c66_1: mbox-c66-1 {
|
|
ti,mbox-rx = <2 0 0>;
|
|
ti,mbox-tx = <3 0 0>;
|
|
};
|
|
};
|
|
|
|
&mailbox0_cluster4 {
|
|
interrupts = <420>;
|
|
|
|
mbox_c71_0: mbox-c71-0 {
|
|
ti,mbox-rx = <0 0 0>;
|
|
ti,mbox-tx = <1 0 0>;
|
|
};
|
|
};
|
|
|
|
&mailbox0_cluster5 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster6 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster7 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster8 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster9 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster10 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster11 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mcu_r5fss0_core0 {
|
|
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
|
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
|
<&mcu_r5fss0_core0_memory_region>;
|
|
};
|
|
|
|
&mcu_r5fss0_core1 {
|
|
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
|
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
|
<&mcu_r5fss0_core1_memory_region>;
|
|
};
|
|
|
|
&main_r5fss0_core0 {
|
|
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
|
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
|
<&main_r5fss0_core0_memory_region>;
|
|
};
|
|
|
|
&main_r5fss0_core1 {
|
|
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
|
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
|
<&main_r5fss0_core1_memory_region>;
|
|
};
|
|
|
|
&main_r5fss1_core0 {
|
|
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
|
|
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
|
<&main_r5fss1_core0_memory_region>;
|
|
};
|
|
|
|
&main_r5fss1_core1 {
|
|
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
|
|
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
|
<&main_r5fss1_core1_memory_region>;
|
|
};
|
|
|
|
&c66_0 {
|
|
mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
|
|
memory-region = <&c66_0_dma_memory_region>,
|
|
<&c66_0_memory_region>;
|
|
};
|
|
|
|
&c66_1 {
|
|
mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
|
|
memory-region = <&c66_1_dma_memory_region>,
|
|
<&c66_1_memory_region>;
|
|
};
|
|
|
|
&c71_0 {
|
|
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
|
|
memory-region = <&c71_0_dma_memory_region>,
|
|
<&c71_0_memory_region>;
|
|
};
|