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075cbae163
Update default AXI, TUN, ARC clock set options: instead of changing only IDIV divider settings adjust also domain PLL settings. Add support of TUN_ROM and TUN_PWM clocks (subclocks of TUNN_PLL) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
42 lines
1.1 KiB
C
42 lines
1.1 KiB
C
/*
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* Synopsys HSDK SDP CGU clock driver dts bindings
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*
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* Copyright (C) 2017 Synopsys
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* Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __DT_BINDINGS_CLK_HSDK_CGU_H_
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#define __DT_BINDINGS_CLK_HSDK_CGU_H_
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#define CLK_ARC_PLL 0
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#define CLK_ARC 1
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#define CLK_DDR_PLL 2
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#define CLK_SYS_PLL 3
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#define CLK_SYS_APB 4
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#define CLK_SYS_AXI 5
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#define CLK_SYS_ETH 6
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#define CLK_SYS_USB 7
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#define CLK_SYS_SDIO 8
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#define CLK_SYS_HDMI 9
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#define CLK_SYS_GFX_CORE 10
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#define CLK_SYS_GFX_DMA 11
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#define CLK_SYS_GFX_CFG 12
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#define CLK_SYS_DMAC_CORE 13
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#define CLK_SYS_DMAC_CFG 14
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#define CLK_SYS_SDIO_REF 15
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#define CLK_SYS_SPI_REF 16
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#define CLK_SYS_I2C_REF 17
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#define CLK_SYS_UART_REF 18
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#define CLK_SYS_EBI_REF 19
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#define CLK_TUN_PLL 20
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#define CLK_TUN_TUN 21
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#define CLK_TUN_ROM 22
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#define CLK_TUN_PWM 23
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#define CLK_HDMI_PLL 24
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#define CLK_HDMI 25
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#endif /* __DT_BINDINGS_CLK_HSDK_CGU_H_ */
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