mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 14:23:00 +00:00
4f0c4be1c3
Configuration variables should have the same meaning independent of the architecture. x86 and ARM both use CONFIG_STACK_SIZE: * x86: U-Boot's runtime stack size during reboot * ARM: max stack size that can be used by U-Boot Rename the x86 configuration variable to CONFIG_STACK_SIZE_REBOOT Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
147 lines
3.6 KiB
C
147 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <handoff.h>
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#include <init.h>
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#include <log.h>
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#include <asm/fsp/fsp_support.h>
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#include <asm/e820.h>
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#include <asm/mrccache.h>
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#include <asm/mtrr.h>
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#include <asm/post.h>
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DECLARE_GLOBAL_DATA_PTR;
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int fsp_scan_for_ram_size(void)
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{
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phys_size_t ram_size = 0;
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const struct hob_header *hdr;
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struct hob_res_desc *res_desc;
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hdr = gd->arch.hob_list;
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while (!end_of_hob(hdr)) {
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if (hdr->type == HOB_TYPE_RES_DESC) {
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res_desc = (struct hob_res_desc *)hdr;
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if (res_desc->type == RES_SYS_MEM ||
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res_desc->type == RES_MEM_RESERVED)
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ram_size += res_desc->len;
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}
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hdr = get_next_hob(hdr);
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}
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gd->ram_size = ram_size;
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post_code(POST_DRAM);
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return 0;
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};
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int dram_init_banksize(void)
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{
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const struct hob_header *hdr;
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struct hob_res_desc *res_desc;
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phys_addr_t low_end;
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uint bank;
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if (!ll_boot_init()) {
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gd->bd->bi_dram[0].start = 0;
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gd->bd->bi_dram[0].size = gd->ram_size;
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mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);
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return 0;
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}
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low_end = 0;
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for (bank = 1, hdr = gd->arch.hob_list;
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bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
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hdr = get_next_hob(hdr)) {
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if (hdr->type != HOB_TYPE_RES_DESC)
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continue;
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res_desc = (struct hob_res_desc *)hdr;
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if (res_desc->type != RES_SYS_MEM &&
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res_desc->type != RES_MEM_RESERVED)
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continue;
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if (res_desc->phys_start < (1ULL << 32)) {
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low_end = max(low_end,
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res_desc->phys_start + res_desc->len);
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continue;
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}
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gd->bd->bi_dram[bank].start = res_desc->phys_start;
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gd->bd->bi_dram[bank].size = res_desc->len;
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mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
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res_desc->len);
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log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start,
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gd->bd->bi_dram[bank].size);
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}
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/* Add the memory below 4GB */
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gd->bd->bi_dram[0].start = 0;
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gd->bd->bi_dram[0].size = low_end;
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mtrr_add_request(MTRR_TYPE_WRBACK, 0, low_end);
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return 0;
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}
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unsigned int install_e820_map(unsigned int max_entries,
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struct e820_entry *entries)
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{
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unsigned int num_entries = 0;
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const struct hob_header *hdr;
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struct hob_res_desc *res_desc;
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hdr = gd->arch.hob_list;
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while (!end_of_hob(hdr)) {
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if (hdr->type == HOB_TYPE_RES_DESC) {
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res_desc = (struct hob_res_desc *)hdr;
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entries[num_entries].addr = res_desc->phys_start;
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entries[num_entries].size = res_desc->len;
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if (res_desc->type == RES_SYS_MEM)
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entries[num_entries].type = E820_RAM;
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else if (res_desc->type == RES_MEM_RESERVED)
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entries[num_entries].type = E820_RESERVED;
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num_entries++;
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}
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hdr = get_next_hob(hdr);
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}
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/* Mark PCIe ECAM address range as reserved */
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entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
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entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
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entries[num_entries].type = E820_RESERVED;
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num_entries++;
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if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
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ulong stack_size;
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stack_size = CONFIG_IS_ENABLED(HAVE_ACPI_RESUME,
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(CONFIG_STACK_SIZE_RESUME), (0));
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/*
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* Everything between U-Boot's stack and ram top needs to be
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* reserved in order for ACPI S3 resume to work.
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*/
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entries[num_entries].addr = gd->start_addr_sp - stack_size;
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entries[num_entries].size = gd->ram_top - gd->start_addr_sp +
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stack_size;
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entries[num_entries].type = E820_RESERVED;
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num_entries++;
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}
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return num_entries;
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}
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#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
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int handoff_arch_save(struct spl_handoff *ho)
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{
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ho->arch.usable_ram_top = fsp_get_usable_lowmem_top(gd->arch.hob_list);
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ho->arch.hob_list = gd->arch.hob_list;
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return 0;
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}
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#endif
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