mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-02-16 14:08:45 +00:00
ea7d3eec1e
This reverts commitd2099587d6. According to TI changing the VDD_CORE while the SoC is running is not allowed, the voltage must be set before the AM62 device reset is released, revert this change therefore. The correct solution would be to program the PMIC during manufactoring according to the speed grade of the SoC. Link: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1318338/am623-booting-from-mmc-failed-after-lowering-vdd_core-to-0-75v/5036508#5036508 Fixes:d2099587d6("board: verdin-am62: set cpu core voltage depending on speed grade") Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
133 lines
3.2 KiB
C
133 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Board specific initialization for Verdin AM62 SoM
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*
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* Copyright 2023 Toradex - https://www.toradex.com/
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*
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*/
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#include <config.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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#include <dm/uclass.h>
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#include <env.h>
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#include <fdt_support.h>
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#include <init.h>
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#include <k3-ddrss.h>
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#include <spl.h>
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#include "../common/tdx-cfg-block.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE);
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if (gd->ram_size < SZ_512M)
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puts("## WARNING: Less than 512MB RAM detected\n");
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return 0;
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}
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/*
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* Avoid relocated U-Boot clash with Linux reserved-memory on 512 MB SoM
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*/
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phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
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{
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return 0x9C000000;
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}
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#if defined(CONFIG_SPL_LOAD_FIT)
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int board_fit_config_name_match(const char *name)
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{
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return 0;
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}
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#endif
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#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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return ft_common_board_setup(blob, bd);
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}
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#endif
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static void select_dt_from_module_version(void)
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{
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char variant[32];
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char *env_variant = env_get("variant");
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int is_wifi = 0;
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if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) {
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/*
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* If we have a valid config block and it says we are a module with
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* Wi-Fi/Bluetooth make sure we use the -wifi device tree.
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*/
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is_wifi = (tdx_hw_tag.prodid == VERDIN_AM62Q_WIFI_BT_IT) ||
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(tdx_hw_tag.prodid == VERDIN_AM62S_512MB_WIFI_BT_IT) ||
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(tdx_hw_tag.prodid == VERDIN_AM62D_1G_WIFI_BT_IT) ||
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(tdx_hw_tag.prodid == VERDIN_AM62Q_2G_WIFI_BT_IT);
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}
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if (is_wifi)
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strlcpy(&variant[0], "wifi", sizeof(variant));
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else
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strlcpy(&variant[0], "nonwifi", sizeof(variant));
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if (strcmp(variant, env_variant)) {
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printf("Setting variant to %s\n", variant);
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env_set("variant", variant);
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}
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}
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int board_late_init(void)
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{
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select_dt_from_module_version();
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return 0;
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}
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#define CTRLMMR_USB0_PHY_CTRL 0x43004008
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#define CTRLMMR_USB1_PHY_CTRL 0x43004018
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#define CORE_VOLTAGE 0x80000000
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#define MCU_CTRL_LFXOSC_32K_BYPASS_VAL BIT(4)
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#ifdef CONFIG_SPL_BOARD_INIT
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void spl_board_init(void)
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{
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u32 val;
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/* Clear USB0_PHY_CTRL_CORE_VOLTAGE */
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/* TI recommends to clear the bit independent of VDDA_CORE_USB */
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val = readl(CTRLMMR_USB0_PHY_CTRL);
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val &= ~(CORE_VOLTAGE);
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writel(val, CTRLMMR_USB0_PHY_CTRL);
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/* Clear USB1_PHY_CTRL_CORE_VOLTAGE */
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val = readl(CTRLMMR_USB1_PHY_CTRL);
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val &= ~(CORE_VOLTAGE);
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writel(val, CTRLMMR_USB1_PHY_CTRL);
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/* We use the 32k FOUT from the Epson RX8130CE RTC chip */
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/* In WKUP_LFOSC0 clear the power down bit and set the bypass bit
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* The bypass bit is required as we provide a CMOS clock signal and
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* the power down seems to be required also in the bypass case
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* despite of the datasheet stating otherwise
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*/
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/* Compare with the AM62 datasheet,
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* Table 7-21. LFXOSC Modes of Operation
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*/
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val = readl(MCU_CTRL_LFXOSC_CTRL);
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val &= ~MCU_CTRL_LFXOSC_32K_DISABLE_VAL;
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val |= MCU_CTRL_LFXOSC_32K_BYPASS_VAL;
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writel(val, MCU_CTRL_LFXOSC_CTRL);
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/* Make sure to mux up to take the SoC 32k from the LFOSC input */
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writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL,
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MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
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}
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#endif
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