mirror of
https://github.com/AsahiLinux/u-boot
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10c4ab898c
In Falcon Boot mode, the fdt blob should be move to the RAM from kernel BSS section. To avoid being cleared by BSS initialisation. SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
165 lines
3.2 KiB
C
165 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*/
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#include <config.h>
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#include <cpu_func.h>
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#include <flash.h>
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#include <image.h>
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#include <init.h>
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#include <net.h>
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#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
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#include <netdev.h>
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#endif
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#include <asm/csr.h>
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#include <asm/global_data.h>
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#include <asm/sbi.h>
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#include <linux/io.h>
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#include <faraday/ftsmc020.h>
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#include <fdtdec.h>
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#include <dm.h>
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#include <spl.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Miscellaneous platform dependent initializations
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*/
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#if IS_ENABLED(CONFIG_MISC_INIT_R)
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int misc_init_r(void)
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{
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long csr_marchid = 0;
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const long mask_64 = 0x8000;
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const long mask_cpu = 0xff;
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char cpu_name[10] = {};
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#if CONFIG_IS_ENABLED(RISCV_SMODE)
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sbi_get_marchid(&csr_marchid);
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#elif CONFIG_IS_ENABLED(RISCV_MMODE)
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csr_marchid = csr_read(CSR_MARCHID);
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#endif
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if (mask_64 & csr_marchid)
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snprintf(cpu_name, sizeof(cpu_name), "ax%lx", (mask_cpu & csr_marchid));
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else
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snprintf(cpu_name, sizeof(cpu_name), "a%lx", (mask_cpu & csr_marchid));
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return env_set("cpu", cpu_name);
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}
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#endif
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int board_init(void)
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{
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gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
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return 0;
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}
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int dram_init(void)
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{
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return fdtdec_setup_mem_size_base();
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}
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int dram_init_banksize(void)
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{
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return fdtdec_setup_memory_banksize();
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}
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#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
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int board_eth_init(struct bd_info *bd)
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{
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return ftmac100_initialize(bd);
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}
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#endif
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ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
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{
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return 0;
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}
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#define ANDES_HW_DTB_ADDRESS 0xF2000000
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void *board_fdt_blob_setup(int *err)
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{
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*err = 0;
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if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) {
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if (fdt_magic((uintptr_t)gd->arch.firmware_fdt_addr) == FDT_MAGIC)
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return (void *)(ulong)gd->arch.firmware_fdt_addr;
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}
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if (fdt_magic(CONFIG_SYS_FDT_BASE) == FDT_MAGIC)
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return (void *)CONFIG_SYS_FDT_BASE;
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return (void *)ANDES_HW_DTB_ADDRESS;
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*err = -EINVAL;
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return NULL;
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}
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#ifdef CONFIG_SPL_BOARD_INIT
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void spl_board_init()
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{
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/* enable v5l2 cache */
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if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
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enable_caches();
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}
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#endif
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int smc_init(void)
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{
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int node = -1;
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const char *compat = "andestech,atfsmc020";
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void *blob = (void *)gd->fdt_blob;
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fdt_addr_t addr;
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struct ftsmc020_bank *regs;
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node = fdt_node_offset_by_compatible(blob, -1, compat);
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if (node < 0)
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return -FDT_ERR_NOTFOUND;
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addr = fdtdec_get_addr_size_auto_noparent(blob, node,
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"reg", 0, NULL, false);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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regs = (struct ftsmc020_bank *)(uintptr_t)addr;
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regs->cr &= ~FTSMC020_BANK_WPROT;
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return 0;
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}
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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smc_init();
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return 0;
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}
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#endif
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#ifdef CONFIG_SPL
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void board_boot_order(u32 *spl_boot_list)
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{
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u8 i;
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u32 boot_devices[] = {
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#ifdef CONFIG_SPL_RAM_SUPPORT
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BOOT_DEVICE_RAM,
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#endif
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#ifdef CONFIG_SPL_MMC
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BOOT_DEVICE_MMC1,
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#endif
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};
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for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
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spl_boot_list[i] = boot_devices[i];
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}
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#endif
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* boot using first FIT config */
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return 0;
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}
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#endif
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