u-boot/arch/microblaze/lib/bdinfo.c
Ovidiu Panait f459986e86 microblaze: add arch_print_bdinfo() implementation
Allow bdinfo command to print icache/dcache information:
U-Boot-mONStR> bdinfo
boot_params = 0x00000000
DRAM bank   = 0x00000000
-> start    = 0x04000000
-> size     = 0x04000000
flashstart  = 0x00000000
flashsize   = 0x00000000
flashoffset = 0x00000000
baudrate    = 9600 bps
relocaddr   = 0x07f76000
reloc off   = 0x02f76000
Build       = 32-bit
current eth = unknown
ethaddr     = (not set)
IP addr     = <NULL>
fdt_blob    = 0x07fec7e0
new_fdt     = 0x00000000
fdt_size    = 0x00000000
lmb_dump_all:
 memory.cnt  = 0x1
 memory[0]      [0x4000000-0x7ffffff], 0x04000000 bytes flags: 0
 reserved.cnt  = 0x1
 reserved[0]    [0x7e94b8c-0x7ffffff], 0x0016b474 bytes flags: 0
devicetree  = embed
icache      = 32 KiB
icache line = 4 Bytes
dcache      = 32 KiB
dcache line = 4 Bytes

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220829170205.1274484-4-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13 11:32:48 +02:00

24 lines
553 B
C

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2022, Ovidiu Panait <ovpanait@gmail.com>
*/
#include <init.h>
#include <asm/cpuinfo.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
void arch_print_bdinfo(void)
{
struct microblaze_cpuinfo *ci = gd_cpuinfo();
if (ci->icache_size) {
bdinfo_print_size("icache", ci->icache_size);
bdinfo_print_size("icache line", ci->icache_line_length);
}
if (ci->dcache_size) {
bdinfo_print_size("dcache", ci->dcache_size);
bdinfo_print_size("dcache line", ci->dcache_line_length);
}
}