mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 13:56:30 +00:00
717ceb63a5
This changes clock definition of SCIF from CONFIG_SYS_CLK_FREQ to CONFIG_SH_SCIF_CLK_FREQ, and clock definition of TMU from CONFIG_SYS_CLK_FREQ to CONFIG_SH_TMU_CLK_FREQ, Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Albert Aribaud <albert.u.boot@aribaud.net>
146 lines
4.1 KiB
C
146 lines
4.1 KiB
C
/*
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* Configuation settings for the bonito board
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*
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* Copyright (C) 2012 Renesas Solutions Corp.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ARMADILLO_800EVA_H
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#define __ARMADILLO_800EVA_H
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#undef DEBUG
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#define CONFIG_ARMV7
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#define CONFIG_R8A7740
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#define CONFIG_RMOBILE
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#define CONFIG_RMOBILE_BOARD_STRING "Armadillo-800EVA Board\n"
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#define CONFIG_SH_GPIO_PFC
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#include <asm/arch/rmobile.h>
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_DFL
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_RUN
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#define CONFIG_CMD_LOADS
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_BOOTZ
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#define CONFIG_OF_LIBFDT
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#define BOARD_LATE_INIT
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTARGS ""
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#define CONFIG_VERSION_VARIABLE
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#undef CONFIG_SHOW_BOOT_PROGRESS
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_USE_ARCH_MEMSET
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#define CONFIG_USE_ARCH_MEMCPY
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#define CONFIG_TMU_TIMER
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#define CONFIG_SYS_DCACHE_OFF
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/* STACK */
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#define CONFIG_SYS_INIT_SP_ADDR 0xE8083000
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#define STACK_AREA_SIZE 0xC000
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#define LOW_LEVEL_MERAM_STACK \
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(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
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/* MEMORY */
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#define ARMADILLO_800EVA_SDRAM_BASE 0x40000000
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#define ARMADILLO_800EVA_SDRAM_SIZE (512 * 1024 * 1024)
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_PROMPT "=> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_PBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE 512
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
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/* SCIF */
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#define CONFIG_SCIF_CONSOLE
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#define CONFIG_CONS_SCIF1
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#define SCIF0_BASE 0xe6c40000
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#define SCIF1_BASE 0xe6c50000
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#define SCIF2_BASE 0xe6c60000
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#define SCIF4_BASE 0xe6c80000
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#define CONFIG_SCIF_A
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#undef CONFIG_SYS_CONSOLE_INFO_QUIET
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#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
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#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
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#define CONFIG_SYS_MEMTEST_START (ARMADILLO_800EVA_SDRAM_BASE)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
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504 * 1024 * 1024)
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#undef CONFIG_SYS_ALT_MEMTEST
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#undef CONFIG_SYS_MEMTEST_SCRATCH
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE
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#define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE)
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#define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
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64 * 1024 * 1024)
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_MONITOR_BASE 0x00000000
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
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#define CONFIG_SYS_GBL_DATA_SIZE (256)
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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#define CONFIG_SYS_TEXT_BASE 0xE80C0000
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/* FLASH */
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_FLASH_BASE 0x00000000
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
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#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
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#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
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#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
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/* ENV setting */
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_ENV_SECT_SIZE (128 * 1024)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
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#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
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/* SH Ether */
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#define CONFIG_NET_MULTI
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x0
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#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000
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#define CONFIG_SH_ETHER_SH7734_MII (0x01)
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_SMSC
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 50000000
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_SYS_HZ 1000
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#endif /* __ARMADILLO_800EVA_H */
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