u-boot/arch/arm/mach-lpc32xx/lowlevel_init.S
Trevor Woerner b3d9a8b185 arm: lpc32xx: move SoC to mach-lpc32xx
Following the example of most other SoCs in arch/$(ARCH)/cpu/$(CPU)/$(SOC)
move the lpc32xx code from arch/arm/cpu/arm926ejs/lpc32xx to
arch/arm/mach-lpc32xx.

Following the checklist from
commit 01f1445630 ("ARM: prepare for moving SoC sources into mach-*"):

    [1] move files from arch/arm/cpu/arm926ejs/lpc32xx to arch/arm/mach-lpx32xx
    [2] add machine entry to arch/arm/Makefile
    [3] remove "obj-y += ..." from arch/arm/cpu/arm926ejs/Makefile
    [4] fix the Kconfig file path in arch/arm/Kconfig
    [5] (no MAINTAINERS update)

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-15 14:47:35 -04:00

44 lines
1,000 B
ArmAsm

/* SPDX-License-Identifier: GPL-2.0+ */
/*
* WORK Microwave work_92105 board low level init
*
* (C) Copyright 2014 DENX Software Engineering GmbH
* Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
*
* Low level init is called from SPL to set up the clocks.
* On entry, the LPC3250 is in Direct Run mode with all clocks
* running at 13 MHz; on exit, ARM clock is 208 MHz, HCLK is
* 104 MHz and PCLK is 13 MHz.
*
* This code must run from SRAM so that the clock changes do
* not prevent it from executing.
*/
.globl lowlevel_init
lowlevel_init:
/* Set ARM, HCLK, PCLK dividers for normal mode */
ldr r0, =0x0000003D
ldr r1, =0x40004040
str r0, [r1]
/* Start HCLK PLL for 208 MHz */
ldr r0, =0x0001401E
ldr r1, =0x40004058
str r0, [r1]
/* wait for HCLK PLL to lock */
1:
ldr r0, [r1]
ands r0, r0, #1
beq 1b
/* switch to normal mode */
ldr r1, =0x40004044
ldr r0, [r1]
orr r0, #0x00000004
str r0, [r1]
/* Return to U-Boot via saved link register */
mov pc, lr