mirror of
https://github.com/AsahiLinux/u-boot
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e92a6b2ee3
EEC is being enabled based on the ddr size populated by SPD data. But not all keystone platforms have SPD data to detect ddr3 size. So, enable ECC using the detected DDR size. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
279 lines
5.7 KiB
C
279 lines
5.7 KiB
C
/*
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* Keystone : Board initialization
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*
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* (C) Copyright 2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include "board.h"
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#include <spl.h>
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#include <exports.h>
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#include <fdt_support.h>
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#include <asm/arch/ddr3.h>
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#include <asm/arch/psc_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/ti-common/ti-aemif.h>
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#include <asm/ti-common/keystone_net.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_TI_AEMIF)
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static struct aemif_config aemif_configs[] = {
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{ /* CS0 */
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.mode = AEMIF_MODE_NAND,
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.wr_setup = 0xf,
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.wr_strobe = 0x3f,
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.wr_hold = 7,
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.rd_setup = 0xf,
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.rd_strobe = 0x3f,
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.rd_hold = 7,
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.turn_around = 3,
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.width = AEMIF_WIDTH_8,
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},
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};
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#endif
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int dram_init(void)
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{
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u32 ddr3_size;
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ddr3_size = ddr3_init();
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gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_MAX_RAM_BANK_SIZE);
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#if defined(CONFIG_TI_AEMIF)
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aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
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#endif
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if (ddr3_size)
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ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
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else
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ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, gd->ram_size >> 30);
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
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#ifndef CONFIG_DM_ETH
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int get_eth_env_param(char *env_name)
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{
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char *env;
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int res = -1;
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env = getenv(env_name);
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if (env)
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res = simple_strtol(env, NULL, 0);
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return res;
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}
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int board_eth_init(bd_t *bis)
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{
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int j;
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int res;
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int port_num;
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char link_type_name[32];
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if (cpu_is_k2g())
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writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
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/* By default, select PA PLL clock as PA clock source */
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#ifndef CONFIG_SOC_K2G
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if (psc_enable_module(KS2_LPSC_PA))
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return -1;
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#endif
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if (psc_enable_module(KS2_LPSC_CPGMAC))
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return -1;
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if (psc_enable_module(KS2_LPSC_CRYPTO))
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return -1;
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if (cpu_is_k2e() || cpu_is_k2l())
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pll_pa_clk_sel();
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port_num = get_num_eth_ports();
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for (j = 0; j < port_num; j++) {
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sprintf(link_type_name, "sgmii%d_link_type", j);
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res = get_eth_env_param(link_type_name);
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if (res >= 0)
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eth_priv_cfg[j].sgmii_link_type = res;
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keystone2_emac_initialize(ð_priv_cfg[j]);
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}
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return 0;
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}
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#endif
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#endif
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#ifdef CONFIG_SPL_BUILD
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void spl_board_init(void)
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{
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spl_init_keystone_plls();
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preloader_console_init();
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}
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u32 spl_boot_device(void)
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{
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#if defined(CONFIG_SPL_SPI_LOAD)
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return BOOT_DEVICE_SPI;
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#else
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puts("Unknown boot device\n");
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hang();
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#endif
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}
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#endif
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, bd_t *bd)
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{
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int lpae;
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char *env;
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char *endp;
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int nbanks;
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u64 size[2];
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u64 start[2];
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int nodeoffset;
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u32 ddr3a_size;
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int unitrd_fixup = 0;
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env = getenv("mem_lpae");
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lpae = env && simple_strtol(env, NULL, 0);
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env = getenv("uinitrd_fixup");
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unitrd_fixup = env && simple_strtol(env, NULL, 0);
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ddr3a_size = 0;
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if (lpae) {
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ddr3a_size = ddr3_get_size();
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if ((ddr3a_size != 8) && (ddr3a_size != 4))
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ddr3a_size = 0;
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}
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nbanks = 1;
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start[0] = bd->bi_dram[0].start;
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size[0] = bd->bi_dram[0].size;
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/* adjust memory start address for LPAE */
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if (lpae) {
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start[0] -= CONFIG_SYS_SDRAM_BASE;
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start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
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}
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if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
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size[1] = ((u64)ddr3a_size - 2) << 30;
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start[1] = 0x880000000;
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nbanks++;
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}
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/* reserve memory at start of bank */
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env = getenv("mem_reserve_head");
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if (env) {
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start[0] += ustrtoul(env, &endp, 0);
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size[0] -= ustrtoul(env, &endp, 0);
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}
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env = getenv("mem_reserve");
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if (env)
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size[0] -= ustrtoul(env, &endp, 0);
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fdt_fixup_memory_banks(blob, start, size, nbanks);
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/* Fix up the initrd */
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if (lpae && unitrd_fixup) {
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int err;
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u32 *prop1, *prop2;
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u64 initrd_start, initrd_end;
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nodeoffset = fdt_path_offset(blob, "/chosen");
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if (nodeoffset >= 0) {
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prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
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"linux,initrd-start", NULL);
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prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
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"linux,initrd-end", NULL);
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if (prop1 && prop2) {
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initrd_start = __be32_to_cpu(*prop1);
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initrd_start -= CONFIG_SYS_SDRAM_BASE;
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initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
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initrd_start = __cpu_to_be64(initrd_start);
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initrd_end = __be32_to_cpu(*prop2);
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initrd_end -= CONFIG_SYS_SDRAM_BASE;
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initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
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initrd_end = __cpu_to_be64(initrd_end);
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err = fdt_delprop(blob, nodeoffset,
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"linux,initrd-start");
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if (err < 0)
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puts("error deleting initrd-start\n");
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err = fdt_delprop(blob, nodeoffset,
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"linux,initrd-end");
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if (err < 0)
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puts("error deleting initrd-end\n");
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err = fdt_setprop(blob, nodeoffset,
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"linux,initrd-start",
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&initrd_start,
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sizeof(initrd_start));
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if (err < 0)
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puts("error adding initrd-start\n");
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err = fdt_setprop(blob, nodeoffset,
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"linux,initrd-end",
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&initrd_end,
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sizeof(initrd_end));
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if (err < 0)
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puts("error adding linux,initrd-end\n");
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}
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}
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}
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return 0;
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}
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void ft_board_setup_ex(void *blob, bd_t *bd)
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{
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int lpae;
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u64 size;
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char *env;
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u64 *reserve_start;
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env = getenv("mem_lpae");
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lpae = env && simple_strtol(env, NULL, 0);
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if (lpae) {
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/*
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* the initrd and other reserved memory areas are
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* embedded in in the DTB itslef. fix up these addresses
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* to 36 bit format
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*/
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reserve_start = (u64 *)((char *)blob +
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fdt_off_mem_rsvmap(blob));
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while (1) {
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*reserve_start = __cpu_to_be64(*reserve_start);
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size = __cpu_to_be64(*(reserve_start + 1));
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if (size) {
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*reserve_start -= CONFIG_SYS_SDRAM_BASE;
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*reserve_start +=
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CONFIG_SYS_LPAE_SDRAM_BASE;
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*reserve_start =
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__cpu_to_be64(*reserve_start);
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} else {
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break;
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}
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reserve_start += 2;
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}
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}
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ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
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}
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#endif /* CONFIG_OF_BOARD_SETUP */
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