mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
186 lines
5.2 KiB
C
186 lines
5.2 KiB
C
/* SPDX-License-Identifier: Intel */
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/*
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* Copyright (C) 2013, Intel Corporation
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* Ported from Intel released Quark UEFI BIOS
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* QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
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*/
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#ifndef _MRC_H_
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#define _MRC_H_
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#define MRC_VERSION 0x0111
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/* architectural definitions */
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#define NUM_CHANNELS 1 /* number of channels */
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#define NUM_RANKS 2 /* number of ranks per channel */
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#define NUM_BYTE_LANES 4 /* number of byte lanes per channel */
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/* software limitations */
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#define MAX_CHANNELS 1
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#define MAX_RANKS 2
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#define MAX_BYTE_LANES 4
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#define MAX_SOCKETS 1
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#define MAX_SIDES 1
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#define MAX_ROWS (MAX_SIDES * MAX_SOCKETS)
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/* Specify DRAM and channel width */
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enum {
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X8, /* DRAM width */
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X16, /* DRAM width & Channel Width */
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X32 /* Channel Width */
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};
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/* Specify DRAM speed */
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enum {
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DDRFREQ_800,
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DDRFREQ_1066
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};
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/* Specify DRAM type */
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enum {
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DDR3,
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DDR3L
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};
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/*
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* density: 0=512Mb, 1=Gb, 2=2Gb, 3=4Gb
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* cl: DRAM CAS Latency in clocks
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* ras: ACT to PRE command period
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* wtr: Delay from start of internal write transaction to internal read command
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* rrd: ACT to ACT command period (JESD79 specific to page size 1K/2K)
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* faw: Four activate window (JESD79 specific to page size 1K/2K)
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*
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* ras/wtr/rrd/faw timings are in picoseconds
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*
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* Refer to JEDEC spec (or DRAM datasheet) when changing these values.
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*/
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struct dram_params {
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uint8_t density;
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uint8_t cl;
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uint32_t ras;
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uint32_t wtr;
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uint32_t rrd;
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uint32_t faw;
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};
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/*
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* Delay configuration for individual signals
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* Vref setting
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* Scrambler seed
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*/
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struct mrc_timings {
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uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
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uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
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uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
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uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
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uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
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uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
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uint32_t wcmd[NUM_CHANNELS];
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uint32_t scrambler_seed;
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/* need to save for the case of frequency change */
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uint8_t ddr_speed;
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};
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/* Boot mode defined as bit mask (1<<n) */
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enum {
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BM_UNKNOWN,
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BM_COLD = 1, /* full training */
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BM_FAST = 2, /* restore timing parameters */
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BM_S3 = 4, /* resume from S3 */
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BM_WARM = 8
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};
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/* MRC execution status */
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#define MRC_SUCCESS 0 /* initialization ok */
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#define MRC_E_MEMTEST 1 /* memtest failed */
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/*
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* Memory Reference Code parameters
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*
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* It includes 3 parts:
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* - input parameters like boot mode and DRAM parameters
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* - context parameters for MRC internal state
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* - output parameters like initialization result and memory size
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*/
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struct mrc_params {
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/* Input parameters */
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uint32_t boot_mode; /* BM_COLD, BM_FAST, BM_WARM, BM_S3 */
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/* DRAM parameters */
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uint8_t dram_width; /* x8, x16 */
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uint8_t ddr_speed; /* DDRFREQ_800, DDRFREQ_1066 */
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uint8_t ddr_type; /* DDR3, DDR3L */
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uint8_t ecc_enables; /* 0, 1 (memory size reduced to 7/8) */
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uint8_t scrambling_enables; /* 0, 1 */
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/* 1, 3 (1'st rank has to be populated if 2'nd rank present) */
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uint32_t rank_enables;
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uint32_t channel_enables; /* 1 only */
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uint32_t channel_width; /* x16 only */
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/* 0, 1, 2 (mode 2 forced if ecc enabled) */
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uint32_t address_mode;
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/* REFRESH_RATE: 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED */
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uint8_t refresh_rate;
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/* SR_TEMP_RANGE: 0=normal, 1=extended, others=RESERVED */
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uint8_t sr_temp_range;
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/*
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* RON_VALUE: 0=34ohm, 1=40ohm, others=RESERVED
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* (select MRS1.DIC driver impedance control)
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*/
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uint8_t ron_value;
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/* RTT_NOM_VALUE: 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */
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uint8_t rtt_nom_value;
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/* RD_ODT_VALUE: 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */
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uint8_t rd_odt_value;
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struct dram_params params;
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/* Internally used context parameters */
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uint32_t board_id; /* board layout (use x8 or x16 memory) */
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uint32_t hte_setup; /* when set hte reconfiguration requested */
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uint32_t menu_after_mrc;
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uint32_t power_down_disable;
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uint32_t tune_rcvn;
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uint32_t channel_size[NUM_CHANNELS];
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uint32_t column_bits[NUM_CHANNELS];
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uint32_t row_bits[NUM_CHANNELS];
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uint32_t mrs1; /* register content saved during training */
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uint8_t first_run;
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/* Output parameters */
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/* initialization result (non zero specifies error code) */
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uint32_t status;
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/* total memory size in bytes (excludes ECC banks) */
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uint32_t mem_size;
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/* training results (also used on input) */
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struct mrc_timings timings;
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};
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/*
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* MRC memory initialization structure
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*
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* post_code: a 16-bit post code of a specific initialization routine
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* boot_path: bitwise or of BM_COLD, BM_FAST, BM_WARM and BM_S3
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* init_fn: real memory initialization routine
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*/
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struct mem_init {
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uint16_t post_code;
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uint16_t boot_path;
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void (*init_fn)(struct mrc_params *mrc_params);
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};
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/* MRC platform data flags */
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#define MRC_FLAG_ECC_EN 0x00000001
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#define MRC_FLAG_SCRAMBLE_EN 0x00000002
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#define MRC_FLAG_MEMTEST_EN 0x00000004
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/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
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#define MRC_FLAG_TOP_TREE_EN 0x00000008
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/* If set ODR signal is asserted to DRAM devices on writes */
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#define MRC_FLAG_WR_ODT_EN 0x00000010
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/**
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* mrc_init - Memory Reference Code initialization entry routine
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*
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* @mrc_params: parameters for MRC
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*/
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void mrc_init(struct mrc_params *mrc_params);
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#endif /* _MRC_H_ */
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