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John Rigby 8a490422be ADS5121: Fix NOR and CPLD ALE timing for rev 2 silicon 
MPC5121 rev 2 silicon has a new register for controlling how long
CS is asserted after deassertion of ALE in multiplexed mode.

The default is to assert CS together with ALE.  The alternative
is to assert CS (ALEN+1)*LPC_CLK clocks after deassertion of ALE.

The default is wrong for the NOR flash and CPLD on the ADS5121.

This patch turns on the alternative for CS0 (NOR) and CS2 (CPLD)
it does so conditionally based on silicon rev 2.0 or greater.

Signed-off-by: Martha J Marx <mmarx@silicontkx.com>
Signed-off-by: John Rigby <jrigby@freescale.com>
2008-08-28 13:36:43 -06:00
..
ads5121.c ADS5121: Fix NOR and CPLD ALE timing for rev 2 silicon 2008-08-28 13:36:43 -06:00
ads5121_diu.c fix DIU for small screens 2008-07-12 13:34:15 -06:00
config.mk [ADS5121] Support for the ADS5121 board 2007-07-27 14:43:59 +02:00
Makefile mpc5121: Move iopin features from board specific to common files. 2008-08-05 20:45:34 -06:00
pci.c MPC5121e ADS PCI support take 3 2008-03-02 21:44:59 +01:00
README Prepare v1.3.4-rc1: Code cleanup, update CHANGELOG, sort Makefile 2008-07-15 22:22:44 +02:00
u-boot.lds Big white-space cleanup. 2008-05-21 00:14:08 +02:00

README 

To configure for the current (Rev 3.x) ADS5121
	make ads5121_config
This will automatically include PCI, the Real Time CLock, add backup flash
ability and set the correct frequency and memory configuration.

To configure for the older Rev 2 ADS5121 type (this will not have PCI)
	make ads5121_rev2_config