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06d336cca2
There are several blocks of registers that are accessed from all over the code on Intel CPUs. These don't currently have their own driver and it is not clear whether having a driver makes sense. An example is the Memory Controller Hub (MCH). We map it to a known location on some Intel chips (mostly those without FSP - Firmware Support Package). Add a new header file for these registers, and move MCH into it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
239 lines
6.1 KiB
C
239 lines
6.1 KiB
C
/*
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* From Coreboot northbridge/intel/sandybridge/northbridge.c
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2011 The Chromium Authors
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/msr.h>
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#include <asm/acpi.h>
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#include <asm/cpu.h>
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#include <asm/intel_regs.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/processor.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/model_206ax.h>
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#include <asm/arch/sandybridge.h>
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int bridge_silicon_revision(struct udevice *dev)
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{
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struct cpuid_result result;
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u16 bridge_id;
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u8 stepping;
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result = cpuid(1);
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stepping = result.eax & 0xf;
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dm_pci_read_config16(dev, PCI_DEVICE_ID, &bridge_id);
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bridge_id &= 0xf0;
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return bridge_id | stepping;
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}
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/*
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* Reserve everything between A segment and 1MB:
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*
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* 0xa0000 - 0xbffff: legacy VGA
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* 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
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* 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
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*/
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static const int legacy_hole_base_k = 0xa0000 / 1024;
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static const int legacy_hole_size_k = 384;
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static int get_pcie_bar(struct udevice *dev, u32 *base, u32 *len)
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{
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u32 pciexbar_reg;
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*base = 0;
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*len = 0;
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dm_pci_read_config32(dev, PCIEXBAR, &pciexbar_reg);
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if (!(pciexbar_reg & (1 << 0)))
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return 0;
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switch ((pciexbar_reg >> 1) & 3) {
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case 0: /* 256MB */
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*base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
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(1 << 28));
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*len = 256 * 1024 * 1024;
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return 1;
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case 1: /* 128M */
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*base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
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(1 << 28) | (1 << 27));
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*len = 128 * 1024 * 1024;
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return 1;
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case 2: /* 64M */
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*base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
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(1 << 28) | (1 << 27) | (1 << 26));
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*len = 64 * 1024 * 1024;
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return 1;
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}
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return 0;
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}
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static void add_fixed_resources(struct udevice *dev, int index)
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{
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u32 pcie_config_base, pcie_config_size;
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if (get_pcie_bar(dev, &pcie_config_base, &pcie_config_size)) {
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debug("Adding PCIe config bar base=0x%08x size=0x%x\n",
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pcie_config_base, pcie_config_size);
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}
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}
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static void northbridge_dmi_init(struct udevice *dev, int rev)
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{
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/* Clear error status bits */
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writel(0xffffffff, DMIBAR_REG(0x1c4));
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writel(0xffffffff, DMIBAR_REG(0x1d0));
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/* Steps prior to DMI ASPM */
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if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
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clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20),
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1 << 21);
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}
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setbits_le32(DMIBAR_REG(0x238), 1 << 29);
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if (rev >= SNB_STEP_D0) {
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setbits_le32(DMIBAR_REG(0x1f8), 1 << 16);
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} else if (rev >= SNB_STEP_D1) {
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clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16);
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setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23));
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}
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/* Enable ASPM on SNB link, should happen before PCH link */
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if ((rev & BASE_REV_MASK) == BASE_REV_SNB)
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setbits_le32(DMIBAR_REG(0xd04), 1 << 4);
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setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0));
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}
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static void northbridge_init(struct udevice *dev, int rev)
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{
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u32 bridge_type;
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add_fixed_resources(dev, 6);
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northbridge_dmi_init(dev, rev);
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bridge_type = readl(MCHBAR_REG(0x5f10));
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bridge_type &= ~0xff;
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if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
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/* Enable Power Aware Interrupt Routing - fixed priority */
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clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4);
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/* 30h for IvyBridge */
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bridge_type |= 0x30;
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} else {
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/* 20h for Sandybridge */
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bridge_type |= 0x20;
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}
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writel(bridge_type, MCHBAR_REG(0x5f10));
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/*
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* Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
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* that BIOS has initialized memory and power management
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*/
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setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1);
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debug("Set BIOS_RESET_CPL\n");
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/* Configure turbo power limits 1ms after reset complete bit */
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mdelay(1);
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set_power_limits(28);
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/*
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* CPUs with configurable TDP also need power limits set
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* in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT.
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*/
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if (cpu_config_tdp_levels()) {
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msr_t msr = msr_read(MSR_PKG_POWER_LIMIT);
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writel(msr.lo, MCHBAR_REG(0x59A0));
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writel(msr.hi, MCHBAR_REG(0x59A4));
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}
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/* Set here before graphics PM init */
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writel(0x00100001, MCHBAR_REG(0x5500));
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}
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static void sandybridge_setup_northbridge_bars(struct udevice *dev)
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{
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/* Set up all hardcoded northbridge BARs */
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debug("Setting up static registers\n");
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dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1);
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dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
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dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
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dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32);
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/* 64MB - busses 0-63 */
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dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
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dm_pci_write_config32(dev, PCIEXBAR + 4,
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(0LL + DEFAULT_PCIEXBAR) >> 32);
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dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1);
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dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
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/* Set C0000-FFFFF to access RAM on both reads and writes */
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dm_pci_write_config8(dev, PAM0, 0x30);
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dm_pci_write_config8(dev, PAM1, 0x33);
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dm_pci_write_config8(dev, PAM2, 0x33);
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dm_pci_write_config8(dev, PAM3, 0x33);
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dm_pci_write_config8(dev, PAM4, 0x33);
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dm_pci_write_config8(dev, PAM5, 0x33);
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dm_pci_write_config8(dev, PAM6, 0x33);
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}
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static int bd82x6x_northbridge_early_init(struct udevice *dev)
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{
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const int chipset_type = SANDYBRIDGE_MOBILE;
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u32 capid0_a;
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u8 reg8;
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/* Device ID Override Enable should be done very early */
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dm_pci_read_config32(dev, 0xe4, &capid0_a);
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if (capid0_a & (1 << 10)) {
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dm_pci_read_config8(dev, 0xf3, ®8);
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reg8 &= ~7; /* Clear 2:0 */
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if (chipset_type == SANDYBRIDGE_MOBILE)
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reg8 |= 1; /* Set bit 0 */
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dm_pci_write_config8(dev, 0xf3, reg8);
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}
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sandybridge_setup_northbridge_bars(dev);
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/* Device Enable */
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dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
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return 0;
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}
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static int bd82x6x_northbridge_probe(struct udevice *dev)
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{
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int rev;
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if (!(gd->flags & GD_FLG_RELOC))
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return bd82x6x_northbridge_early_init(dev);
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rev = bridge_silicon_revision(dev);
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northbridge_init(dev, rev);
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return 0;
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}
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static const struct udevice_id bd82x6x_northbridge_ids[] = {
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{ .compatible = "intel,bd82x6x-northbridge" },
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{ }
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};
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U_BOOT_DRIVER(bd82x6x_northbridge_drv) = {
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.name = "bd82x6x_northbridge",
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.id = UCLASS_NORTHBRIDGE,
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.of_match = bd82x6x_northbridge_ids,
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.probe = bd82x6x_northbridge_probe,
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};
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