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https://github.com/AsahiLinux/u-boot
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85 lines
2.4 KiB
C
85 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* Authors: Timur Tabi <timur@freescale.com>
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*
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* FSL DIU Framebuffer driver
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <command.h>
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#include <log.h>
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#include <linux/ctype.h>
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#include <asm/io.h>
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#include <stdio_dev.h>
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#include <video_fb.h>
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#include <fsl_diu_fb.h>
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#define PMUXCR_ELBCDIU_MASK 0xc0000000
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#define PMUXCR_ELBCDIU_NOR16 0x80000000
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#define PMUXCR_ELBCDIU_DIU 0x40000000
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/*
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* DIU Area Descriptor
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*
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* Note that we need to byte-swap the value before it's written to the AD
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* register. So even though the registers don't look like they're in the same
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* bit positions as they are on the MPC8610, the same value is written to the
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* AD register on the MPC8610 and on the P1022.
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*/
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#define AD_BYTE_F 0x10000000
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#define AD_ALPHA_C_SHIFT 25
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#define AD_BLUE_C_SHIFT 23
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#define AD_GREEN_C_SHIFT 21
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#define AD_RED_C_SHIFT 19
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#define AD_PIXEL_S_SHIFT 16
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#define AD_COMP_3_SHIFT 12
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#define AD_COMP_2_SHIFT 8
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#define AD_COMP_1_SHIFT 4
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#define AD_COMP_0_SHIFT 0
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/*
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* Variables used by the DIU/LBC switching code. It's safe to makes these
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* global, because the DIU requires DDR, so we'll only run this code after
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* relocation.
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*/
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static u32 pmuxcr;
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void diu_set_pixel_clock(unsigned int pixclock)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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unsigned long speed_ccb, temp;
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u32 pixval;
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speed_ccb = get_bus_freq(0);
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temp = 1000000000 / pixclock;
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temp *= 1000;
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pixval = speed_ccb / temp;
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debug("DIU pixval = %u\n", pixval);
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/* Modify PXCLK in GUTS CLKDVDR */
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temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
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out_be32(&gur->clkdvdr, temp); /* turn off clock */
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out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
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}
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int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 pixel_format;
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pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
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(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
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(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
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(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
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(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
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printf("DIU: Switching to %ux%u\n", xres, yres);
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/* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
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clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
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pmuxcr = in_be32(&gur->pmuxcr);
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return fsl_diu_init(xres, yres, pixel_format, 0);
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}
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