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99c7cc58e1
Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
471 lines
14 KiB
C
471 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018-2019 NXP
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*/
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#include <common.h>
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#include <errno.h>
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#include <log.h>
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#include <asm/io.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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static unsigned int g_cdd_rr_max[4];
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static unsigned int g_cdd_rw_max[4];
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static unsigned int g_cdd_wr_max[4];
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static unsigned int g_cdd_ww_max[4];
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void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
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{
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int i = 0;
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for (i = 0; i < num; i++) {
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reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
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ddrc_cfg++;
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}
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}
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#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
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void ddrc_inline_ecc_scrub(unsigned int start_address,
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unsigned int range_address)
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{
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unsigned int tmp;
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/* Step1: Enable quasi-dynamic programming */
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reg32_write(DDRC_SWCTL(0), 0x00000000);
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/* Step2: Set ECCCFG1.ecc_parity_region_lock to 1 */
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reg32setbit(DDRC_ECCCFG1(0), 0x4);
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/* Step3: Block the AXI ports from taking the transaction */
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reg32_write(DDRC_PCTRL_0(0), 0x0);
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/* Step4: Set scrub start address */
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reg32_write(DDRC_SBRSTART0(0), start_address);
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/* Step5: Set scrub range address */
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reg32_write(DDRC_SBRRANGE0(0), range_address);
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/* Step6: Set scrub_mode to write */
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reg32_write(DDRC_SBRCTL(0), 0x00000014);
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/* Step7: Set the desired pattern through SBRWDATA0 registers */
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reg32_write(DDRC_SBRWDATA0(0), 0x55aa55aa);
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/* Step8: Enable the SBR by programming SBRCTL.scrub_en=1 */
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reg32setbit(DDRC_SBRCTL(0), 0x0);
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/* Step9: Poll SBRSTAT.scrub_done=1 */
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tmp = reg32_read(DDRC_SBRSTAT(0));
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while (tmp != 0x00000002)
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tmp = reg32_read(DDRC_SBRSTAT(0)) & 0x2;
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/* Step10: Poll SBRSTAT.scrub_busy=0 */
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tmp = reg32_read(DDRC_SBRSTAT(0));
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while (tmp != 0x0)
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tmp = reg32_read(DDRC_SBRSTAT(0)) & 0x1;
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/* Step11: Disable SBR by programming SBRCTL.scrub_en=0 */
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clrbits_le32(DDRC_SBRCTL(0), 0x1);
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/* Step12: Prepare for normal scrub operation(Read) and set scrub_interval*/
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reg32_write(DDRC_SBRCTL(0), 0x100);
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/* Step13: Enable the SBR by programming SBRCTL.scrub_en=1 */
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reg32_write(DDRC_SBRCTL(0), 0x101);
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/* Step14: Enable AXI ports by programming */
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reg32_write(DDRC_PCTRL_0(0), 0x1);
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/* Step15: Disable quasi-dynamic programming */
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reg32_write(DDRC_SWCTL(0), 0x00000001);
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}
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void ddrc_inline_ecc_scrub_end(unsigned int start_address,
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unsigned int range_address)
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{
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/* Step1: Enable quasi-dynamic programming */
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reg32_write(DDRC_SWCTL(0), 0x00000000);
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/* Step2: Block the AXI ports from taking the transaction */
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reg32_write(DDRC_PCTRL_0(0), 0x0);
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/* Step3: Set scrub start address */
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reg32_write(DDRC_SBRSTART0(0), start_address);
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/* Step4: Set scrub range address */
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reg32_write(DDRC_SBRRANGE0(0), range_address);
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/* Step5: Disable SBR by programming SBRCTL.scrub_en=0 */
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clrbits_le32(DDRC_SBRCTL(0), 0x1);
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/* Step6: Prepare for normal scrub operation(Read) and set scrub_interval */
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reg32_write(DDRC_SBRCTL(0), 0x100);
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/* Step7: Enable the SBR by programming SBRCTL.scrub_en=1 */
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reg32_write(DDRC_SBRCTL(0), 0x101);
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/* Step8: Enable AXI ports by programming */
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reg32_write(DDRC_PCTRL_0(0), 0x1);
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/* Step9: Disable quasi-dynamic programming */
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reg32_write(DDRC_SWCTL(0), 0x00000001);
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}
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#endif
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void __weak board_dram_ecc_scrub(void)
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{
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}
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void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr,
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unsigned int mr_data)
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{
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unsigned int tmp;
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/*
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* 1. Poll MRSTAT.mr_wr_busy until it is 0.
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* This checks that there is no outstanding MR transaction.
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* No writes should be performed to MRCTRL0 and MRCTRL1 if
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* MRSTAT.mr_wr_busy = 1.
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*/
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do {
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tmp = reg32_read(DDRC_MRSTAT(0));
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} while (tmp & 0x1);
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/*
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* 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and
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* (for MRWs) MRCTRL1.mr_data to define the MR transaction.
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*/
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reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4));
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reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data);
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reg32setbit(DDRC_MRCTRL0(0), 31);
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}
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unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
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{
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unsigned int tmp;
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reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1);
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do {
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tmp = reg32_read(DDRC_MRSTAT(0));
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} while (tmp & 0x1);
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reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
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reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8));
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reg32setbit(DDRC_MRCTRL0(0), 31);
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do {
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tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
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} while ((tmp & 0x8) == 0);
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tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
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tmp = tmp & 0xff;
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reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
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return tmp;
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}
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static unsigned int look_for_max(unsigned int data[], unsigned int addr_start,
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unsigned int addr_end)
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{
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unsigned int i, imax = 0;
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for (i = addr_start; i <= addr_end; i++) {
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if (((data[i] >> 7) == 0) && data[i] > imax)
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imax = data[i];
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}
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return imax;
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}
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void get_trained_CDD(u32 fsp)
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{
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unsigned int i, ddr_type, tmp;
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unsigned int cdd_cha[12], cdd_chb[12];
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unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max;
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unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max;
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ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
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if (ddr_type == 0x20) {
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for (i = 0; i < 6; i++) {
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tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54013 + i) * 4);
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cdd_cha[i * 2] = tmp & 0xff;
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cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff;
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}
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for (i = 0; i < 7; i++) {
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tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x5402c + i) * 4);
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if (i == 0) {
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cdd_cha[0] = (tmp >> 8) & 0xff;
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} else if (i == 6) {
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cdd_cha[11] = tmp & 0xff;
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} else {
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cdd_chb[i * 2 - 1] = tmp & 0xff;
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cdd_chb[i * 2] = (tmp >> 8) & 0xff;
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}
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}
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cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1);
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cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5);
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cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9);
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cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11);
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cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1);
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cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5);
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cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9);
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cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11);
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g_cdd_rr_max[fsp] =
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cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max;
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g_cdd_rw_max[fsp] =
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cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max;
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g_cdd_wr_max[fsp] =
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cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max;
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g_cdd_ww_max[fsp] =
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cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max;
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} else {
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unsigned int ddr4_cdd[64];
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for (i = 0; i < 29; i++) {
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tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54012 + i) * 4);
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ddr4_cdd[i * 2] = tmp & 0xff;
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ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff;
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}
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g_cdd_rr_max[fsp] = look_for_max(ddr4_cdd, 1, 12);
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g_cdd_ww_max[fsp] = look_for_max(ddr4_cdd, 13, 24);
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g_cdd_rw_max[fsp] = look_for_max(ddr4_cdd, 25, 40);
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g_cdd_wr_max[fsp] = look_for_max(ddr4_cdd, 41, 56);
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}
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}
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void update_umctl2_rank_space_setting(unsigned int pstat_num)
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{
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unsigned int i, ddr_type;
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unsigned int addr_slot, rdata, tmp, tmp_t;
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unsigned int ddrc_w2r, ddrc_r2w, ddrc_wr_gap, ddrc_rd_gap;
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ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
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for (i = 0; i < pstat_num; i++) {
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addr_slot = i ? (i + 1) * 0x1000 : 0;
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if (ddr_type == 0x20) {
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/* update r2w:[13:8], w2r:[5:0] */
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rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
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ddrc_w2r = rdata & 0x3f;
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if (is_imx8mp())
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tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
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else
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tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
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ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
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ddrc_r2w = (rdata >> 8) & 0x3f;
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if (is_imx8mp())
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tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
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else
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tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
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ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
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tmp_t = (rdata & 0xffffc0c0) | (ddrc_r2w << 8) | ddrc_w2r;
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reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
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} else {
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/* update w2r:[5:0] */
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rdata = reg32_read(DDRC_DRAMTMG9(0) + addr_slot);
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ddrc_w2r = rdata & 0x3f;
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if (is_imx8mp())
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tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
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else
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tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
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ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
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tmp_t = (rdata & 0xffffffc0) | ddrc_w2r;
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reg32_write((DDRC_DRAMTMG9(0) + addr_slot), tmp_t);
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/* update r2w:[13:8] */
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rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
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ddrc_r2w = (rdata >> 8) & 0x3f;
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if (is_imx8mp())
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tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
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else
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tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
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ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
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tmp_t = (rdata & 0xffffc0ff) | (ddrc_r2w << 8);
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reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
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}
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if (!is_imx8mq()) {
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/*
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* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static)
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*/
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rdata = reg32_read(DDRC_RANKCTL(0) + addr_slot);
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ddrc_wr_gap = (rdata >> 8) & 0xf;
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if (is_imx8mp())
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tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1);
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else
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tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1) + 1;
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ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
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ddrc_rd_gap = (rdata >> 4) & 0xf;
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if (is_imx8mp())
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tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1);
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else
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tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1) + 1;
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ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
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tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
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reg32_write((DDRC_RANKCTL(0) + addr_slot), tmp_t);
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}
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}
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if (is_imx8mq()) {
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/* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
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rdata = reg32_read(DDRC_RANKCTL(0));
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ddrc_wr_gap = (rdata >> 8) & 0xf;
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tmp = ddrc_wr_gap + (g_cdd_ww_max[0] >> 1) + 1;
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ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
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ddrc_rd_gap = (rdata >> 4) & 0xf;
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tmp = ddrc_rd_gap + (g_cdd_rr_max[0] >> 1) + 1;
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ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
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tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
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reg32_write(DDRC_RANKCTL(0), tmp_t);
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}
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}
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int ddr_init(struct dram_timing_info *dram_timing)
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{
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unsigned int tmp, initial_drate, target_freq;
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int ret;
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debug("DDRINFO: start DRAM init\n");
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/* Step1: Follow the power up procedure */
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if (is_imx8mq()) {
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reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F);
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
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reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
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} else {
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F);
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
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}
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debug("DDRINFO: cfg clk\n");
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/* change the clock source of dram_apb_clk_root: source 4 800MHz /4 = 200MHz */
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clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) |
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CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
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/* disable iso */
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reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
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reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
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initial_drate = dram_timing->fsp_msg[0].drate;
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/* default to the frequency point 0 clock */
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ddrphy_init_set_dfi_clk(initial_drate);
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/* D-aasert the presetn */
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
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/* Step2: Program the dwc_ddr_umctl2 registers */
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debug("DDRINFO: ddrc config start\n");
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ddr_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
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debug("DDRINFO: ddrc config done\n");
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/* Step3: De-assert reset signal(core_ddrc_rstn & aresetn_n) */
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
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/*
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* Step4: Disable auto-refreshes, self-refresh, powerdown, and
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* assertion of dfi_dram_clk_disable by setting RFSHCTL3.dis_auto_refresh = 1,
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* PWRCTL.powerdown_en = 0, and PWRCTL.selfref_en = 0, PWRCTL.en_dfi_dram_clk_disable = 0
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*/
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reg32_write(DDRC_DBG1(0), 0x00000000);
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reg32_write(DDRC_RFSHCTL3(0), 0x0000001);
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reg32_write(DDRC_PWRCTL(0), 0xa0);
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/* if ddr type is LPDDR4, do it */
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tmp = reg32_read(DDRC_MSTR(0));
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if (tmp & (0x1 << 5) && !is_imx8mn())
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reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */
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/* determine the initial boot frequency */
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target_freq = reg32_read(DDRC_MSTR2(0)) & 0x3;
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target_freq = (tmp & (0x1 << 29)) ? target_freq : 0x0;
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/* Step5: Set SWCT.sw_done to 0 */
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reg32_write(DDRC_SWCTL(0), 0x00000000);
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/* Set the default boot frequency point */
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clrsetbits_le32(DDRC_DFIMISC(0), (0x1f << 8), target_freq << 8);
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/* Step6: Set DFIMISC.dfi_init_complete_en to 0 */
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|
clrbits_le32(DDRC_DFIMISC(0), 0x1);
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|
|
|
/* Step7: Set SWCTL.sw_done to 1; need to polling SWSTAT.sw_done_ack */
|
|
reg32_write(DDRC_SWCTL(0), 0x00000001);
|
|
do {
|
|
tmp = reg32_read(DDRC_SWSTAT(0));
|
|
} while ((tmp & 0x1) == 0x0);
|
|
|
|
/*
|
|
* Step8 ~ Step13: Start PHY initialization and training by
|
|
* accessing relevant PUB registers
|
|
*/
|
|
debug("DDRINFO:ddrphy config start\n");
|
|
|
|
ret = ddr_cfg_phy(dram_timing);
|
|
if (ret)
|
|
return ret;
|
|
|
|
debug("DDRINFO: ddrphy config done\n");
|
|
|
|
/*
|
|
* step14 CalBusy.0 =1, indicates the calibrator is actively
|
|
* calibrating. Wait Calibrating done.
|
|
*/
|
|
do {
|
|
tmp = reg32_read(DDRPHY_CalBusy(0));
|
|
} while ((tmp & 0x1));
|
|
|
|
debug("DDRINFO:ddrphy calibration done\n");
|
|
|
|
/* Step15: Set SWCTL.sw_done to 0 */
|
|
reg32_write(DDRC_SWCTL(0), 0x00000000);
|
|
|
|
/* Apply rank-to-rank workaround */
|
|
update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1);
|
|
|
|
/* Step16: Set DFIMISC.dfi_init_start to 1 */
|
|
setbits_le32(DDRC_DFIMISC(0), (0x1 << 5));
|
|
|
|
/* Step17: Set SWCTL.sw_done to 1; need to polling SWSTAT.sw_done_ack */
|
|
reg32_write(DDRC_SWCTL(0), 0x00000001);
|
|
do {
|
|
tmp = reg32_read(DDRC_SWSTAT(0));
|
|
} while ((tmp & 0x1) == 0x0);
|
|
|
|
/* Step18: Polling DFISTAT.dfi_init_complete = 1 */
|
|
do {
|
|
tmp = reg32_read(DDRC_DFISTAT(0));
|
|
} while ((tmp & 0x1) == 0x0);
|
|
|
|
/* Step19: Set SWCTL.sw_done to 0 */
|
|
reg32_write(DDRC_SWCTL(0), 0x00000000);
|
|
|
|
/* Step20: Set DFIMISC.dfi_init_start to 0 */
|
|
clrbits_le32(DDRC_DFIMISC(0), (0x1 << 5));
|
|
|
|
/* Step21: optional */
|
|
|
|
/* Step22: Set DFIMISC.dfi_init_complete_en to 1 */
|
|
setbits_le32(DDRC_DFIMISC(0), 0x1);
|
|
|
|
/* Step23: Set PWRCTL.selfref_sw to 0 */
|
|
clrbits_le32(DDRC_PWRCTL(0), (0x1 << 5));
|
|
|
|
/* Step24: Set SWCTL.sw_done to 1; need polling SWSTAT.sw_done_ack */
|
|
reg32_write(DDRC_SWCTL(0), 0x00000001);
|
|
do {
|
|
tmp = reg32_read(DDRC_SWSTAT(0));
|
|
} while ((tmp & 0x1) == 0x0);
|
|
|
|
/* Step25: Wait for dwc_ddr_umctl2 to move to normal operating mode by monitoring
|
|
* STAT.operating_mode signal */
|
|
do {
|
|
tmp = reg32_read(DDRC_STAT(0));
|
|
} while ((tmp & 0x3) != 0x1);
|
|
|
|
/* Step26: Set back register in Step4 to the original values if desired */
|
|
reg32_write(DDRC_RFSHCTL3(0), 0x0000000);
|
|
|
|
/* enable port 0 */
|
|
reg32_write(DDRC_PCTRL_0(0), 0x00000001);
|
|
debug("DDRINFO: ddrmix config done\n");
|
|
|
|
board_dram_ecc_scrub();
|
|
|
|
/* enable selfref_en by default */
|
|
setbits_le32(DDRC_PWRCTL(0), 0x1);
|
|
|
|
/* save the dram timing config into memory */
|
|
dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr)
|
|
{
|
|
return 4 * paddr_apb_from_ctlr;
|
|
}
|