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https://github.com/AsahiLinux/u-boot
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ddfeb0aaf4
Clock Manager driver will be called to reconfigure all the clocks setting based on user input. The input are passed to Preloader through handoff files Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Pavel Machek <pavel@denx.de>
205 lines
8.1 KiB
C
205 lines
8.1 KiB
C
/*
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CLOCK_MANAGER_H_
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#define _CLOCK_MANAGER_H_
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typedef struct {
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/* main group */
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uint32_t main_vco_base;
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uint32_t mpuclk;
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uint32_t mainclk;
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uint32_t dbgatclk;
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uint32_t mainqspiclk;
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uint32_t mainnandsdmmcclk;
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uint32_t cfg2fuser0clk;
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uint32_t maindiv;
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uint32_t dbgdiv;
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uint32_t tracediv;
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uint32_t l4src;
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/* peripheral group */
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uint32_t peri_vco_base;
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uint32_t emac0clk;
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uint32_t emac1clk;
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uint32_t perqspiclk;
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uint32_t pernandsdmmcclk;
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uint32_t perbaseclk;
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uint32_t s2fuser1clk;
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uint32_t perdiv;
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uint32_t gpiodiv;
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uint32_t persrc;
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/* sdram pll group */
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uint32_t sdram_vco_base;
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uint32_t ddrdqsclk;
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uint32_t ddr2xdqsclk;
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uint32_t ddrdqclk;
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uint32_t s2fuser2clk;
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} cm_config_t;
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extern void cm_basic_init(const cm_config_t *cfg);
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struct socfpga_clock_manager {
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u32 ctrl;
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u32 bypass;
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u32 inter;
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u32 intren;
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u32 dbctrl;
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u32 stat;
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u32 _pad_0x18_0x3f[10];
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u32 mainpllgrp;
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u32 perpllgrp;
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u32 sdrpllgrp;
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u32 _pad_0xe0_0x200[72];
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u32 main_pll_vco;
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u32 main_pll_misc;
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u32 main_pll_mpuclk;
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u32 main_pll_mainclk;
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u32 main_pll_dbgatclk;
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u32 main_pll_mainqspiclk;
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u32 main_pll_mainnandsdmmcclk;
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u32 main_pll_cfgs2fuser0clk;
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u32 main_pll_en;
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u32 main_pll_maindiv;
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u32 main_pll_dbgdiv;
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u32 main_pll_tracediv;
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u32 main_pll_l4src;
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u32 main_pll_stat;
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u32 main_pll__pad_0x38_0x40[2];
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u32 per_pll_vco;
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u32 per_pll_misc;
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u32 per_pll_emac0clk;
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u32 per_pll_emac1clk;
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u32 per_pll_perqspiclk;
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u32 per_pll_pernandsdmmcclk;
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u32 per_pll_perbaseclk;
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u32 per_pll_s2fuser1clk;
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u32 per_pll_en;
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u32 per_pll_div;
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u32 per_pll_gpiodiv;
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u32 per_pll_src;
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u32 per_pll_stat;
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u32 per_pll__pad_0x34_0x40[3];
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u32 sdr_pll_vco;
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u32 sdr_pll_ctrl;
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u32 sdr_pll_ddrdqsclk;
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u32 sdr_pll_ddr2xdqsclk;
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u32 sdr_pll_ddrdqclk;
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u32 sdr_pll_s2fuser2clk;
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u32 sdr_pll_en;
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u32 sdr_pll_stat;
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};
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#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
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#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
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#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
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#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
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#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
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#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
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#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
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#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
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#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
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#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
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#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380)
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#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
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#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
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#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
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#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
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#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
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#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
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#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
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#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
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#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
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#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
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#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
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#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
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#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
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#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
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#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
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#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
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#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
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#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
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#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
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#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
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#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
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#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) \
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(((x) << 0) & 0x000001ff)
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#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
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#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
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#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
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#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) \
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(((x) << 0) & 0x000001ff)
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#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
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#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
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#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
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#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
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#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
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#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
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#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
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#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
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#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
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#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
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#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
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#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
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#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
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#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
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#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
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#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
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#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
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#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
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#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
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#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
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#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
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#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
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#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
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#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
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#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
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#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
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#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
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#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
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#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
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#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
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#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
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#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
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#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
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#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
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#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
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#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
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#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
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#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
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#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
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#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
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#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
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#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
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#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
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#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
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#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
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#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
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#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
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#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
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#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
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#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
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#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
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#define MAIN_VCO_BASE \
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(CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \
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CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER))
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#define PERI_VCO_BASE \
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(CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \
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CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \
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CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER))
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#define SDR_VCO_BASE \
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(CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \
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CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \
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CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER))
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#endif /* _CLOCK_MANAGER_H_ */
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