u-boot/arch/arm/dts/zynq-zc770-xm010.dts
Jagan Teki 7b0d345981 dts: zc770-xm010: Enable zynq qspi controller node
Enabled zynq qspi controller node for zc770-xm010 board.

=> sf probe 0 -- bus1 for selecting qspi controller
=> sf probe 1 -- bus0 for selecting spi controller

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2015-10-25 20:17:02 +05:30

98 lines
1.3 KiB
Text

/*
* Xilinx ZC770 XM010 board DTS
*
* Copyright (C) 2013 - 2015 Xilinx, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynq-7000.dtsi"
/ {
compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
model = "Xilinx Zynq";
aliases {
ethernet0 = &gem0;
i2c0 = &i2c0;
serial0 = &uart1;
spi0 = &qspi;
spi1 = &spi1;
};
chosen {
bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
linux,stdout-path = &uart1;
stdout-path = &uart1;
};
memory {
device_type = "memory";
reg = <0x0 0x40000000>;
};
usb_phy0: phy0 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};
&spi1 {
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
flash@0 {
compatible = "sst25wf080";
reg = <1>;
spi-max-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <1>;
partition@test {
label = "spi-flash";
reg = <0x0 0x100000>;
};
};
};
&qspi {
status = "okay";
};
&can0 {
status = "okay";
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
ethernet_phy: ethernet-phy@7 {
reg = <7>;
};
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
m24c02_eeprom@52 {
compatible = "at,24c02";
reg = <0x52>;
};
};
&sdhci0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
usb-phy = <&usb_phy0>;
};