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c9935c9925
lowlevel_init of SH was corrected to use the write/readXX macro. However, there was a problem that was not able to be compiled partially. This patch corrected this. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
239 lines
4.9 KiB
ArmAsm
239 lines
4.9 KiB
ArmAsm
/*
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* Copyright (C) 2007
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*
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* Copyright (C) 2007
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* Kenati Technologies, Inc.
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*
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* board/ms7722se/lowlevel_init.S
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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/*
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* Board specific low level init code, called _very_ early in the
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* startup sequence. Relocation to SDRAM has not happened yet, no
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* stack is available, bss section has not been initialised, etc.
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*
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* (Note: As no stack is available, no subroutines can be called...).
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*/
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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/*
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* Cache Control Register
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* Instruction Cache Invalidate
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*/
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write32 CCR_A, CCR_D
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/*
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* Address of MMU Control Register
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* TI == TLB Invalidate bit
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*/
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write32 MMUCR_A, MMUCR_D
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/* Address of Power Control Register 0 */
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write32 MSTPCR0_A, MSTPCR0_D
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/* Address of Power Control Register 2 */
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write32 MSTPCR2_A, MSTPCR2_D
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write16 SBSCR_A, SBSCR_D
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write16 PSCR_A, PSCR_D
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/* 0xA4520004 (Watchdog Control / Status Register) */
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! write16 RWTCSR_A, RWTCSR_D_1 /* 0xA507 -> timer_STOP/WDT_CLK=max */
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/* 0xA4520000 (Watchdog Count Register) */
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write16 RWTCNT_A, RWTCNT_D /*0x5A00 -> Clear */
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/* 0xA4520004 (Watchdog Control / Status Register) */
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write16 RWTCSR_A, RWTCSR_D_2 /* 0xA504 -> timer_STOP/CLK=500ms */
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/* 0xA4150000 Frequency control register */
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write32 FRQCR_A, FRQCR_D
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write32 CCR_A, CCR_D_2
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bsc_init:
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write16 PSELA_A, PSELA_D
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write16 DRVCR_A, DRVCR_D
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write16 PCCR_A, PCCR_D
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write16 PECR_A, PECR_D
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write16 PJCR_A, PJCR_D
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write16 PXCR_A, PXCR_D
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write32 CMNCR_A, CMNCR_D
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write32 CS0BCR_A, CS0BCR_D
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write32 CS2BCR_A, CS2BCR_D
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write32 CS4BCR_A, CS4BCR_D
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write32 CS5ABCR_A, CS5ABCR_D
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write32 CS5BBCR_A, CS5BBCR_D
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write32 CS6ABCR_A, CS6ABCR_D
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write32 CS0WCR_A, CS0WCR_D
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write32 CS2WCR_A, CS2WCR_D
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write32 CS4WCR_A, CS4WCR_D
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write32 CS5AWCR_A, CS5AWCR_D
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write32 CS5BWCR_A, CS5BWCR_D
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write32 CS6AWCR_A, CS6AWCR_D
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! SDRAM initialization
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write32 SDCR_A, SDCR_D
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write32 SDWCR_A, SDWCR_D
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write32 SDPCR_A, SDPCR_D
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write32 RTCOR_A, RTCOR_D
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write32 RTCSR_A, RTCSR_D
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write8 SDMR3_A, SDMR3_D
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! BL bit off (init = ON) (?!?)
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stc sr, r0 ! BL bit off(init=ON)
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mov.l SR_MASK_D, r1
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and r1, r0
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ldc r0, sr
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rts
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mov #0, r0
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.align 2
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CCR_A: .long CCR
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MMUCR_A: .long MMUCR
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MSTPCR0_A: .long MSTPCR0
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MSTPCR2_A: .long MSTPCR2
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SBSCR_A: .long SBSCR
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PSCR_A: .long PSCR
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RWTCSR_A: .long RWTCSR
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RWTCNT_A: .long RWTCNT
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FRQCR_A: .long FRQCR
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CCR_D: .long 0x00000800
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CCR_D_2: .long 0x00000103
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MMUCR_D: .long 0x00000004
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MSTPCR0_D: .long 0x00001001
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MSTPCR2_D: .long 0xffffffff
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FRQCR_D: .long 0x07022538
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PSELA_A: .long 0xa405014E
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PSELA_D: .word 0x0A10
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.align 2
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DRVCR_A: .long 0xa405018A
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DRVCR_D: .word 0x0554
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.align 2
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PCCR_A: .long 0xa4050104
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PCCR_D: .word 0x8800
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.align 2
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PECR_A: .long 0xa4050108
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PECR_D: .word 0x0000
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.align 2
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PJCR_A: .long 0xa4050110
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PJCR_D: .word 0x1000
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.align 2
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PXCR_A: .long 0xa4050148
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PXCR_D: .word 0x0AAA
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.align 2
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CMNCR_A: .long CMNCR
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CMNCR_D: .long 0x00000013
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CS0BCR_A: .long CS0BCR ! Flash bank 1
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CS0BCR_D: .long 0x24920400
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CS2BCR_A: .long CS2BCR ! SRAM
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CS2BCR_D: .long 0x24920400
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CS4BCR_A: .long CS4BCR ! FPGA, PCMCIA, USB, ext slot
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CS4BCR_D: .long 0x24920400
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CS5ABCR_A: .long CS5ABCR ! Ext slot
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CS5ABCR_D: .long 0x24920400
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CS5BBCR_A: .long CS5BBCR ! USB controller
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CS5BBCR_D: .long 0x24920400
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CS6ABCR_A: .long CS6ABCR ! Ethernet
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CS6ABCR_D: .long 0x24920400
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CS0WCR_A: .long CS0WCR
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CS0WCR_D: .long 0x00000300
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CS2WCR_A: .long CS2WCR
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CS2WCR_D: .long 0x00000300
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CS4WCR_A: .long CS4WCR
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CS4WCR_D: .long 0x00000300
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CS5AWCR_A: .long CS5AWCR
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CS5AWCR_D: .long 0x00000300
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CS5BWCR_A: .long CS5BWCR
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CS5BWCR_D: .long 0x00000300
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CS6AWCR_A: .long CS6AWCR
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CS6AWCR_D: .long 0x00000300
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SDCR_A: .long SBSC_SDCR
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SDCR_D: .long 0x00020809
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SDWCR_A: .long SBSC_SDWCR
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SDWCR_D: .long 0x00164d0d
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SDPCR_A: .long SBSC_SDPCR
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SDPCR_D: .long 0x00000087
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RTCOR_A: .long SBSC_RTCOR
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RTCOR_D: .long 0xA55A0034
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RTCSR_A: .long SBSC_RTCSR
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RTCSR_D: .long 0xA55A0010
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SDMR3_A: .long 0xFE500180
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SDMR3_D: .long 0x0
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.align 1
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SBSCR_D: .word 0x0040
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PSCR_D: .word 0x0000
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RWTCSR_D_1: .word 0xA507
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RWTCSR_D_2: .word 0xA507
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RWTCNT_D: .word 0x5A00
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.align 2
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SR_MASK_D: .long 0xEFFFFF0F
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