mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-19 19:28:36 +00:00
7a8e9bed17
Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engström, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board
112 lines
3.1 KiB
ArmAsm
112 lines
3.1 KiB
ArmAsm
/*
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* U-boot - i386 Startup Code
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*
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* Copyright (c) 2002, 2003 Omicron Ceti AB, Daniel Engström <denaiel@omicron.se>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#define BOOT_SEG 0xffff0000 /* linear segment of boot code */
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#define a32 .byte 0x67;
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#define o32 .byte 0x66;
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.section .start16, "ax"
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.code16
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.globl start16
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start16:
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/* First we let the BSP do some early initialization
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* this code have to map the flash to its final position
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*/
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mov $board_init16_ret, %bp
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jmp board_init16
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board_init16_ret:
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/* Turn of cache (this might require a 486-class CPU) */
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movl %cr0, %eax
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orl $0x60000000,%eax
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movl %eax, %cr0
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wbinvd
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/* load the descriptor tables */
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o32 cs lidt idt_ptr
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o32 cs lgdt gdt_ptr
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/* Now, we enter protected mode */
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movl %cr0, %eax
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orl $1,%eax
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movl %eax, %cr0
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/* Flush the prefetch queue */
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jmp ff
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ff:
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/* Finally jump to the 32bit initialization code */
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movw $code32start, %ax
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movw %ax,%bp
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o32 cs ljmp *(%bp)
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/* 48-bit far pointer */
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code32start:
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.long _start /* offset */
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.word 0x10 /* segment */
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idt_ptr:
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.word 0 /* limit */
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.long 0 /* base */
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gdt_ptr:
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.word 0x30 /* limit (48 bytes = 6 GDT entries) */
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.long BOOT_SEG + gdt /* base */
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/* The GDT table ...
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*
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* Selector Type
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* 0x00 NULL
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* 0x08 Unused
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* 0x10 32bit code
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* 0x18 32bit data/stack
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* 0x20 16bit code
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* 0x28 16bit data/stack
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*/
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gdt:
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.word 0, 0, 0, 0 /* NULL */
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.word 0, 0, 0, 0 /* unused */
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.word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */
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.word 0 /* base address = 0 */
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.word 0x9B00 /* code read/exec */
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.word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */
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.word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */
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.word 0x0 /* base address = 0 */
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.word 0x9300 /* data read/write */
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.word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */
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.word 0xFFFF /* 64kb */
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.word 0 /* base address = 0 */
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.word 0x9b00 /* data read/write */
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.word 0x0010 /* granularity = 1 (+5th nibble of limit) */
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.word 0xFFFF /* 64kb */
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.word 0 /* base address = 0 */
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.word 0x9300 /* data read/write */
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.word 0x0010 /* granularity = 1 (+5th nibble of limit) */
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