mirror of
https://github.com/AsahiLinux/u-boot
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f87696afa0
All boards have been converted to use mdio node that's why move ethernet phys under mdio node too. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/6c60f5d29b9d9992bd0130fd263c8ed13cb8166c.1697115523.git.michal.simek@amd.com
442 lines
10 KiB
Text
442 lines
10 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller
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*
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* (C) Copyright 2021 - 2022, Xilinx, Inc.
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* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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model = "ZynqMP System Controller on vp-x-a2785-00 board RevA";
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compatible = "xlnx,zynqmp-vp-x-a2785-00-revA",
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"xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp";
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aliases {
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ethernet0 = &gem0;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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mmc0 = &sdhci0;
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serial0 = &uart0;
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serial1 = &dcc;
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spi0 = &qspi;
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usb0 = &usb0;
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usb1 = &usb1;
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nvmem0 = &eeprom;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0 0 0 0x80000000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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j383 {
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label = "j383";
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gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
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linux,code = <BTN_MISC>;
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wakeup-source;
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autorepeat;
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};
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};
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leds {
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compatible = "gpio-leds";
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heartbeat-led { /* ds52 */
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label = "heartbeat";
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gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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si5332_0: si5332_0 { /* ps_ref_clk - u142 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <33333333>;
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};
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si5332_1: si5332_1 { /* clk0_sgmii - u142 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <33333333>; /* FIXME */
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};
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si5332_2: si5332_2 { /* clk1_usb - u142 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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};
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&qspi { /* MIO 0-5 */
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status = "okay";
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flash@0 {
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compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-tx-bus-width = <4>; /* maybe 4 here */
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spi-rx-bus-width = <4>;
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spi-max-frequency = <108000000>;
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partition@0 { /* for testing purpose */
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label = "qspi";
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reg = <0 0x4000000>;
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};
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};
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};
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&sdhci1 { /* sd MIO 45-51 */
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status = "okay";
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no-1-8-v;
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disable-wp;
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xlnx,mio-bank = <1>;
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};
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&uart0 { /* uart0 MIO38-39 */
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status = "okay";
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bootph-all;
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};
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&gem0 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "sgmii"; /* DTG generates this properly 1512 */
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is-internal-pcspma;
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/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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/* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
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phy0: ethernet-phy@0 { /* u131 - M88e1512 */
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reg = <0>;
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};
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};
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};
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&gpio {
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status = "okay";
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gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
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"QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */
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"SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "", "", /* 10 - 14 */
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"", "", "", "", "", /* 15 - 19 */
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"", "", "", "", "", /* 20 - 24 */
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"", "", "", "", "", /* 25 - 29 */
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"", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
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"LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
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"", "", "ETH_RESET_B", "", "", /* 40 - 44 */
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"SD1_CD", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
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"SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
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"USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
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"USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
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"", "", "", "", "", /* 65 - 69 */
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"", "", "", "", "", /* 70 - 74 */
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"", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
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"", "", /* 78 - 79 */
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"", "", "", "", "", /* 80 - 84 */
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"", "", "", "", "", /* 85 - 89 */
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"", "", "", "", "", /* 90 - 94 */
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"", "", "", "", "", /* 95 - 99 */
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"", "", "", "", "", /* 100 - 104 */
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"", "", "", "", "", /* 105 - 109 */
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"", "", "", "", "", /* 110 - 114 */
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"", "", "", "", "", /* 115 - 119 */
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"", "", "", "", "", /* 120 - 124 */
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"", "", "", "", "", /* 125 - 129 */
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"", "", "", "", "", /* 130 - 134 */
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"", "", "", "", "", /* 135 - 139 */
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"", "", "", "", "", /* 140 - 144 */
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"", "", "", "", "", /* 145 - 149 */
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"", "", "", "", "", /* 150 - 154 */
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"", "", "", "", "", /* 155 - 159 */
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"", "", "", "", "", /* 160 - 164 */
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"", "", "", "", "", /* 165 - 169 */
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"", "", "", ""; /* 170 - 173 */
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};
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&i2c0 { /* MIO 34-35 - can't stay here */
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status = "okay";
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clock-frequency = <400000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c0_default>;
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pinctrl-1 = <&pinctrl_i2c0_gpio>;
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scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller; /* interrupt not connected */
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#gpio-cells = <2>;
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gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */
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"", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */
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"", "", "", "VCCINT_FAULT_B", /* 10 - 13 */
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"VCCINT_VRHOT_B", "", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
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};
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i2c-mux@74 { /* u33 */
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x74>;
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/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
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pmbus_i2c: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/* On connector J325 */
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reg_vccint: tps53681@60 { /* u266 - 0xc0 */
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compatible = "ti,tps53681", "ti,tps53679";
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reg = <0x60>;
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};
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reg_vcc1v1_lp4: tps544@d { /* u85 */
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compatible = "ti,tps544b25";
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reg = <0xd>;
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};
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reg_mgtyavcc: tps544@10 { /* u274 */
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compatible = "ti,tps544b25";
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reg = <0x10>;
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};
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reg_mgtyavtt: tps544@11 { /* u275 */
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compatible = "ti,tps544b25";
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reg = <0x11>;
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};
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reg_vccaux: tps544@12 { /* u276 */
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compatible = "ti,tps544b25";
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reg = <0x12>;
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};
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reg_vcc_cpm: tps544@14 { /* u272 */
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compatible = "ti,tps544b25";
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reg = <0x14>;
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};
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reg_util_3v3: tps544@1d { /* u278 */
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compatible = "ti,tps544b25";
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reg = <0x1d>;
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};
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};
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pmbus1_ina226_i2c: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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/* FIXME check alerts coming to SC */
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vcc_cpm: ina226@44 { /* u273 */
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compatible = "ti,ina226";
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reg = <0x44>;
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shunt-resistor = <1000>;
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};
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};
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i2c@2 { /* NC */ /* FIXME maybe remove */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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};
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pcie_smbus: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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};
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pcie2_smbus: i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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};
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i2c@5 { /* NC */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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};
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user_si570: i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <6>;
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};
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/* 7 unused */
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};
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};
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&i2c1 { /* i2c1 MIO 36-37 */
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status = "okay";
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clock-frequency = <400000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1_default>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-mux@74 { /* u35 */
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x74>;
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/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
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dc_i2c: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/* Use for storing information about SC board */
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eeprom: eeprom@54 { /* u34 - m24128 16kB */
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compatible = "st,24c128", "atmel,24c128";
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reg = <0x54>; /* & 0x5c */
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};
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si570_ref_clk: clock-generator@5d { /* u32 */
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#clock-cells = <0>;
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compatible = "silabs,si570";
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reg = <0x5d>;
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temperature-stability = <50>;
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factory-fout = <33333333>;
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clock-frequency = <33333333>;
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clock-output-names = "ref_clk";
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silabs,skip-recall;
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};
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};
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i2c@1 { /* NC - FIXME */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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i2c@2 { /* NC - FIXME */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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};
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i2c@3 { /* NC - FIXME */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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};
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lpddr4_si570_clk2_i2c: i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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lpddr4_clk2: clock-generator@60 { /* u3 */
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#clock-cells = <0>;
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compatible = "silabs,si570";
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reg = <0x60>;
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temperature-stability = <50>;
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factory-fout = <200000000>;
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clock-frequency = <200000000>;
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clock-output-names = "lpddr4_clk2";
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};
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};
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lpddr4_si570_clk1_i2c: i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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lpddr4_clk1: clock-generator@60 { /* u248 */
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#clock-cells = <0>;
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compatible = "silabs,si570";
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reg = <0x60>;
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temperature-stability = <50>;
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factory-fout = <200000000>;
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clock-frequency = <200000000>;
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clock-output-names = "lpddr4_clk1";
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};
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};
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/* 6-7 unused */
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};
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};
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&usb0 { /* MIO52 - MIO63 */
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status = "okay";
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phy-names = "usb3-phy";
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phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
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};
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&psgtr {
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status = "okay";
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/* sgmii, usb3 */
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clocks = <&si5332_1>, <&si5332_2>;
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clock-names = "ref0", "ref1";
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};
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&dwc3_0 {
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status = "okay";
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dr_mode = "peripheral";
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snps,dis_u2_susphy_quirk;
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snps,dis_u3_susphy_quirk;
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maximum-speed = "super-speed";
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};
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&xilinx_ams {
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status = "okay";
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};
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&ams_ps {
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status = "okay";
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};
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&ams_pl {
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status = "okay";
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};
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&pinctrl0 {
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status = "okay";
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pinctrl_i2c0_default: i2c0-default {
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mux {
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groups = "i2c0_8_grp";
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function = "i2c0";
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};
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conf {
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groups = "i2c0_8_grp";
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_i2c0_gpio: i2c0-gpio {
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mux {
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groups = "gpio0_34_grp", "gpio0_35_grp";
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function = "gpio0";
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};
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conf {
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groups = "gpio0_34_grp", "gpio0_35_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_i2c1_default: i2c1-default {
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mux {
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groups = "i2c1_9_grp";
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function = "i2c1";
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};
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conf {
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groups = "i2c1_9_grp";
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_i2c1_gpio: i2c1-gpio {
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mux {
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groups = "gpio0_36_grp", "gpio0_37_grp";
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function = "gpio0";
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};
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conf {
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groups = "gpio0_36_grp", "gpio0_37_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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};
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};
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