mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
3429071700
Commit 9d803d8c mistakenly changed some constants
from 0x300 into 300 - this patch fixes it.
Pointed out by Tom Evans <tom@ceos.com.au>, see
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/51992 for
details.
Signed-off-by: Wolfgang Denk <wd@denx.de>
146 lines
3.4 KiB
ArmAsm
146 lines
3.4 KiB
ArmAsm
/*
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* (C) Copyright 2006 DENX Software Engineering
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/pxa-regs.h>
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DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
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.macro wait time
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ldr r2, =OSCR
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mov r3, #0
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str r3, [r2]
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0:
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ldr r3, [r2]
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cmp r3, \time
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bls 0b
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.endm
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.globl lowlevel_init
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lowlevel_init:
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/* Set up GPIO pins first */
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mov r10, lr
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/* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */
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ldr r0, =GPIO97
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ldr r1, =0x801
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str r1, [r0]
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ldr r0, =GPIO98
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ldr r1, =0x801
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str r1, [r0]
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/* tebrandt - ASCR, clear the RDH bit */
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ldr r0, =ASCR
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ldr r1, [r0]
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bic r1, r1, #0x80000000
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str r1, [r0]
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mem_init:
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/* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
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ldr r0, =ACCR
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ldr r1, [r0]
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orr r1, r1, #0x3000
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str r1, [r0]
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ldr r1, [r0]
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/* 2. Programm MDCNFG, leaving DMCEN de-asserted */
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ldr r0, =MDCNFG
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ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
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/* ldr r1, =0x80000403 */
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str r1, [r0]
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ldr r1, [r0] /* delay until written */
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/* 3. wait nop power up waiting period (200ms)
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* optimization: Steps 4+6 can be done during this
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*/
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wait #0x300
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/* 4. Perform an initial Rcomp-calibration cycle */
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ldr r0, =RCOMP
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ldr r1, =0x80000000
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str r1, [r0]
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ldr r1, [r0] /* delay until written */
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/* missing: program for automatic rcomp evaluation cycles */
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/* 5. DDR DRAM strobe delay calibration */
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ldr r0, =DDR_HCAL
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ldr r1, =0x88000007
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str r1, [r0]
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wait #5
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ldr r1, [r0] /* delay until written */
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/* Set MDMRS */
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ldr r0, =MDMRS
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ldr r1, =0x60000033
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str r1, [r0]
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wait #300
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/* Configure MDREFR */
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ldr r0, =MDREFR
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ldr r1, =0x00000006
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str r1, [r0]
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ldr r1, [r0]
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/* Enable the dynamic memory controller */
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ldr r0, =MDCNFG
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ldr r1, [r0]
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orr r1, r1, #MDCNFG_DMCEN
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str r1, [r0]
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#ifndef CONFIG_SYS_SKIP_DRAM_SCRUB
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/* scrub/init SDRAM if enabled/present */
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ldr r8, =CONFIG_SYS_DRAM_BASE /* base address of SDRAM (CONFIG_SYS_DRAM_BASE) */
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ldr r9, =CONFIG_SYS_DRAM_SIZE /* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) */
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mov r0, #0 /* scrub with 0x0000:0000 */
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mov r1, #0
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mov r2, #0
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mov r3, #0
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mov r4, #0
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mov r5, #0
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mov r6, #0
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mov r7, #0
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10: /* fastScrubLoop */
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subs r9, r9, #32 /* 8 words/line */
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stmia r8!, {r0-r7}
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beq 15f
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b 10b
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#endif /* CONFIG_SYS_SKIP_DRAM_SCRUB */
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15:
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/* Mask all interrupts */
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mov r1, #0
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mcr p6, 0, r1, c1, c0, 0 @ ICMR
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/* Disable software and data breakpoints */
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mov r0, #0
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mcr p15,0,r0,c14,c8,0 /* ibcr0 */
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mcr p15,0,r0,c14,c9,0 /* ibcr1 */
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mcr p15,0,r0,c14,c4,0 /* dbcon */
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/* Enable all debug functionality */
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mov r0,#0x80000000
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mcr p14,0,r0,c10,c0,0 /* dcsr */
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endlowlevel_init:
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mov pc, lr
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