mirror of
https://github.com/AsahiLinux/u-boot
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f1683aa73c
This allows us to use the same DRAM init function on all archs. Add a dummy function for arc, which does not use DRAM init here. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Dummy function on nios2] Signed-off-by: Tom Rini <trini@konsulko.com>
118 lines
2.4 KiB
C
118 lines
2.4 KiB
C
/*
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* (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
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* (C) Copyright 2009 Dave Srl www.dave.eu
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/bitops.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/mpc512x.h>
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#include <fdt_support.h>
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#ifdef CONFIG_MISC_INIT_R
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#include <i2c.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->ram_size = fixed_sdram(NULL, NULL, 0);
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return 0;
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}
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int misc_init_r(void)
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{
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u32 tmp;
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/* we use I2C-2 for on-board eeprom */
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i2c_set_bus_num(2);
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tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE);
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printf("FPGA: %u-%u.%u.%u\n",
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(tmp & 0xFF000000) >> 24,
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(tmp & 0x00FF0000) >> 16,
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(tmp & 0x0000FF00) >> 8,
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tmp & 0x000000FF
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);
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return 0;
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}
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static iopin_t ioregs_init[] = {
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/*
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* FEC
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*/
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/* FEC on PSCx_x*/
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{
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offsetof(struct ioctrl512x, io_control_psc0_0), 5, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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{
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offsetof(struct ioctrl512x, io_control_psc1_0), 10, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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{
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offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/*
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* DIU
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*/
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/* FUNC2=DIU CLK */
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{
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offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
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},
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/* FUNC2=DIU_HSYNC */
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{
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offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
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{
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offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/*
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* On board SRAM
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*/
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/* FUNC2=/LPC CS6 */
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{
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offsetof(struct ioctrl512x, io_control_j1850_rx), 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(1) | IO_PIN_ST(1) | IO_PIN_DS(3)
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},
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};
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int checkboard (void)
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{
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puts("Board: ARIA\n");
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/* initialize function mux & slew rate IO inter alia on IO Pins */
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iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
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return 0;
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}
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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return 0;
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}
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#endif /* CONFIG_OF_BOARD_SETUP */
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