u-boot/board/freescale/ls1043aqds/README
Vladimir Oltean 77b11f7604 net: replace the "xfi" phy-mode with "10gbase-r"
As part of the effort of making U-Boot work with the same device tree as
Linux, there is an issue with the "xfi" phy-mode. To be precise, in
Linux there was a discussion (for those who have time to read:
https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/)

which led to a patch:
https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881

TL;DR: "xfi" was standardized in Linux as "10gbase-r".

This patch changes the relevant occurrences in U-Boot to use "10gbase-r"
instead of "xfi" wherever applicable.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-09-28 18:50:56 +03:00

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Overview
--------
The LS1043A Development System (QDS) is a high-performance computing,
evaluation, and development platform that supports the QorIQ LS1043A
LayerScape Architecture processor. The LS1043AQDS provides SW development
platform for the Freescale LS1043A processor series, with a complete
debugging environment.
LS1043A SoC Overview
--------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
SoC overview.
LS1043AQDS board Overview
-----------------------
- SERDES Connections, 4 lanes supporting:
- PCI Express - 3.0
- SGMII, SGMII 2.5
- QSGMII
- SATA 3.0
- 10GBase-R
- DDR Controller
- 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s
-IFC/Local Bus
- One in-socket 128 MB NOR flash 16-bit data bus
- One 512 MB NAND flash with ECC support
- PromJet Port
- FPGA connection
- USB 3.0
- Three high speed USB 3.0 ports
- First USB 3.0 port configured as Host with Type-A connector
- The other two USB 3.0 ports configured as OTG with micro-AB connector
- SDHC port connects directly to an adapter card slot, featuring:
- Optional clock feedback paths, and optional high-speed voltage translation assistance
- SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC
- eMMC memory devices
- DSPI: Onboard support for three SPI flash memory devices
- 4 I2C controllers
- One SATA onboard connectors
- UART
- Two 4-pin serial ports at up to 115.2 Kbit/s
- Two DB9 D-Type connectors supporting one Serial port each
- ARM JTAG support
Memory map from core's view
----------------------------
Start Address End Address Description Size
0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB
0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB
0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB
0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB
0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
Booting Options
---------------
a) Promjet Boot
b) NOR boot
c) NAND boot
d) SD boot
e) QSPI boot