mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 02:08:38 +00:00
f98457d70a
Corstone1000 is a platform from arm, which includes pre verified Corstone SSE710 sub-system that combines Cortex-A and Cortex-M processors [0]. This code adds the support for the Cortex-A35 implementation at host side, it contains also the necessary bits to support the Corstone 1000 FVP (Fixed Virtual Platform) [1] and also the FPGA MPS3 board implementation of this platform. [2] 0: https://developer.arm.com/documentation/102360/0000 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps 2: https://developer.arm.com/documentation/dai0550/c/ Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
91 lines
1.8 KiB
C
91 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* (C) Copyright 2022 ARM Limited
|
|
* (C) Copyright 2022 Linaro
|
|
* Rui Miguel Silva <rui.silva@linaro.org>
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <dm.h>
|
|
#include <netdev.h>
|
|
#include <dm/platform_data/serial_pl01x.h>
|
|
#include <asm/armv8/mmu.h>
|
|
#include <asm/global_data.h>
|
|
|
|
static struct mm_region corstone1000_mem_map[] = {
|
|
{
|
|
/* CVM */
|
|
.virt = 0x02000000UL,
|
|
.phys = 0x02000000UL,
|
|
.size = 0x02000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
/* QSPI */
|
|
.virt = 0x08000000UL,
|
|
.phys = 0x08000000UL,
|
|
.size = 0x08000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
/* Host Peripherals */
|
|
.virt = 0x1A000000UL,
|
|
.phys = 0x1A000000UL,
|
|
.size = 0x26000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
/* USB */
|
|
.virt = 0x40200000UL,
|
|
.phys = 0x40200000UL,
|
|
.size = 0x00100000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
/* ethernet */
|
|
.virt = 0x40100000UL,
|
|
.phys = 0x40100000UL,
|
|
.size = 0x00100000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
/* OCVM */
|
|
.virt = 0x80000000UL,
|
|
.phys = 0x80000000UL,
|
|
.size = 0x80000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
/* List terminator */
|
|
0,
|
|
}
|
|
};
|
|
|
|
struct mm_region *mem_map = corstone1000_mem_map;
|
|
|
|
int board_init(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
int dram_init(void)
|
|
{
|
|
gd->ram_size = PHYS_SDRAM_1_SIZE;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int dram_init_banksize(void)
|
|
{
|
|
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
|
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void reset_cpu(ulong addr)
|
|
{
|
|
}
|