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https://github.com/AsahiLinux/u-boot
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3498cc9775
The irqroute.asl file is already common enough to all x86 platforms. Platform ASL files need only provide a irqroute.h to describe how internal PCI devices and PCIe downstream port devices' INTx pins are routed to which PIRQ pin. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
211 lines
6.2 KiB
Text
211 lines
6.2 KiB
Text
/*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
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*
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* Modified from coreboot src/soc/intel/baytrail/acpi/southcluster.asl
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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Device (PCI0)
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{
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Name(_HID, EISAID("PNP0A08")) /* PCIe */
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Name(_CID, EISAID("PNP0A03")) /* PCI */
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Name(_ADR, 0)
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Name(_BBN, 0)
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Name(MCRS, ResourceTemplate()
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{
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/* Bus Numbers */
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WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
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/* IO Region 0 */
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
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/* PCI Config Space */
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IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
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/* IO Region 1 */
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
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/* VGA memory (0xa0000-0xbffff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
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0x00020000, , , ASEG)
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/* OPROM reserved (0xc0000-0xc3fff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
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0x00004000, , , OPR0)
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/* OPROM reserved (0xc4000-0xc7fff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
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0x00004000, , , OPR1)
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/* OPROM reserved (0xc8000-0xcbfff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
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0x00004000, , , OPR2)
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/* OPROM reserved (0xcc000-0xcffff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
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0x00004000, , , OPR3)
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/* OPROM reserved (0xd0000-0xd3fff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
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0x00004000, , , OPR4)
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/* OPROM reserved (0xd4000-0xd7fff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
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0x00004000, , , OPR5)
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/* OPROM reserved (0xd8000-0xdbfff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
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0x00004000, , , OPR6)
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/* OPROM reserved (0xdc000-0xdffff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
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0x00004000, , , OPR7)
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/* BIOS Extension (0xe0000-0xe3fff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
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0x00004000, , , ESG0)
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/* BIOS Extension (0xe4000-0xe7fff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
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0x00004000, , , ESG1)
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/* BIOS Extension (0xe8000-0xebfff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
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0x00004000, , , ESG2)
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/* BIOS Extension (0xec000-0xeffff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000ec000, 0x000effff, 0x00000000,
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0x00004000, , , ESG3)
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/* System BIOS (0xf0000-0xfffff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
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0x00010000, , , FSEG)
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/* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, , , PMEM)
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/* High PCI Memory Region */
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QwordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, , , UMEM)
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})
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Method(_CRS, 0, Serialized)
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{
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/* Update PCI resource area */
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CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
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CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
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CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
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/*
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* Hardcode TOLM to 2GB for now as BayTrail FSP uses this value.
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*
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* TODO: for generic usage, read TOLM value from register, or
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* from global NVS (not implemented by U-Boot yet).
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*/
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Store(0x80000000, PMIN)
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Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
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Add(Subtract(PMAX, PMIN), 1, PLEN)
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/* Update High PCI resource area */
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CreateQwordField(MCRS, ^UMEM._MIN, UMIN)
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CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
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CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
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/* Set base address to 48GB and allocate 16GB for PCI space */
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Store(0xc00000000, UMIN)
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Store(0x400000000, ULEN)
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Add(UMIN, Subtract(ULEN, 1), UMAX)
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Return (MCRS)
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}
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/* Device Resource Consumption */
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Device (PDRC)
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{
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Name(_HID, EISAID("PNP0C02"))
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Name(_UID, 1)
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Name(PDRS, ResourceTemplate() {
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Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
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Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
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Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
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Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
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Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
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Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
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Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
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Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
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})
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/* Current Resource Settings */
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Method(_CRS, 0, Serialized)
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{
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Return (PDRS)
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}
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}
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Method(_OSC, 4)
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{
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/* Check for proper GUID */
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If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
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/* Let OS control everything */
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Return (Arg3)
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} Else {
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/* Unrecognized UUID */
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CreateDWordField(Arg3, 0, CDW1)
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Or(CDW1, 4, CDW1)
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Return (Arg3)
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}
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}
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/* LPC Bridge 0:1f.0 */
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#include "lpc.asl"
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/* USB EHCI 0:1d.0 */
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#include "usb.asl"
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/* USB XHCI 0:14.0 */
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#include "xhci.asl"
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/* IRQ routing for each PCI device */
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#include <asm/acpi/irqroute.asl>
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}
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