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Split the SATA clock enabling function and add PCI express clock enabling function. The SATA clock enabling function starts up the 100MHz SATA reference PLL in ENET_PLL register, but the code can be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull this code into separate function. Moreover, add the PCIe clock enabling code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> |
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clock.h | ||
crm_regs.h | ||
gpio.h | ||
hab.h | ||
imx-regs.h | ||
iomux.h | ||
mx6-ddr.h | ||
mx6-pins.h | ||
mx6dl-ddr.h | ||
mx6dl_pins.h | ||
mx6q-ddr.h | ||
mx6q_pins.h | ||
mx6sl_pins.h | ||
mxc_hdmi.h | ||
sys_proto.h |