mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 08:31:03 +00:00
045474be5e
Apple SoCs have an integrated NVMe controller that isn't connected over a PCIe bus. In preparation for adding support for this NVMe controller, split out the PCI support into its own file. This file is selected through a new CONFIG_NVME_PCI Kconfig option, so do a wholesale replacement of CONFIG_NVME with CONFIG_NVME_PCI. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on: Macbook Air M1 Tested-by: Simon Glass <sjg@chromium.org>
82 lines
2.5 KiB
Text
82 lines
2.5 KiB
Text
CONFIG_ARM=y
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CONFIG_TARGET_LS1043ARDB=y
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CONFIG_SYS_TEXT_BASE=0x60100000
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CONFIG_SYS_MALLOC_LEN=0x120000
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_ENV_SIZE=0x20000
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CONFIG_NXP_ESBC=y
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CONFIG_SYS_I2C_MXC_I2C1=y
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CONFIG_SYS_I2C_MXC_I2C2=y
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CONFIG_SYS_I2C_MXC_I2C3=y
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CONFIG_SYS_I2C_MXC_I2C4=y
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CONFIG_DM_GPIO=y
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CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
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CONFIG_FSL_LS_PPA=y
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_REMAKE_ELF=y
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CONFIG_MP=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_BOOTDELAY=10
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
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CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;"
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CONFIG_MISC_INIT_R=y
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CONFIG_CMD_IMLS=y
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CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
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CONFIG_CMD_DM=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_NAND=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_CACHE=y
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CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
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CONFIG_OF_CONTROL=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_DM=y
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# CONFIG_DDR_SPD is not set
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CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
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CONFIG_MPC8XXX_GPIO=y
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CONFIG_DM_I2C=y
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CONFIG_SPL_SYS_I2C_LEGACY=y
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CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x53
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CONFIG_FSL_ESDHC=y
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CONFIG_MTD=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_SST=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_VITESSE=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_FMAN_ENET=y
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CONFIG_SYS_FMAN_FW_ADDR=0x60900000
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CONFIG_NVME_PCI=y
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CONFIG_PCI=y
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CONFIG_PCIE_LAYERSCAPE_RC=y
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CONFIG_SYS_QE_FW_ADDR=0x60940000
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CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_RSA=y
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CONFIG_SPL_RSA=y
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CONFIG_RSA_SOFTWARE_EXP=y
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CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
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