mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-17 16:53:06 +00:00
0b8e6f8411
Add QSPI NAND device node to the Microchip PolarFire SoC Icicle kit device tree. The Winbond NAND flash memory can be connected to the Icicle Kit by using the Mikroe Flash 5 click board and the Pi 3 Click shield. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rick Chen <rick@andestech.com>
132 lines
2.2 KiB
Text
132 lines
2.2 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Copyright (C) 2021-2022 Microchip Technology Inc.
|
|
* Padmarao Begari <padmarao.begari@microchip.com>
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "microchip-mpfs.dtsi"
|
|
|
|
/* Clock frequency (in Hz) of the rtcclk */
|
|
#define RTCCLK_FREQ 1000000
|
|
|
|
/ {
|
|
model = "Microchip PolarFire-SoC Icicle Kit";
|
|
compatible = "microchip,mpfs-icicle-reference-rtlv2210",
|
|
"microchip,mpfs-icicle-kit", "microchip,mpfs";
|
|
|
|
aliases {
|
|
serial1 = &uart1;
|
|
ethernet0 = &mac1;
|
|
spi0 = &qspi;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial1";
|
|
};
|
|
|
|
cpus {
|
|
timebase-frequency = <RTCCLK_FREQ>;
|
|
};
|
|
|
|
ddrc_cache_lo: memory@80000000 {
|
|
device_type = "memory";
|
|
reg = <0x0 0x80000000 0x0 0x40000000>;
|
|
status = "okay";
|
|
};
|
|
|
|
ddrc_cache_hi: memory@1040000000 {
|
|
device_type = "memory";
|
|
reg = <0x10 0x40000000 0x0 0x40000000>;
|
|
status = "okay";
|
|
};
|
|
|
|
reserved-memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
hss_payload: region@BFC00000 {
|
|
reg = <0x0 0xBFC00000 0x0 0x400000>;
|
|
no-map;
|
|
};
|
|
};
|
|
};
|
|
|
|
&uart1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&mmc {
|
|
status = "okay";
|
|
|
|
bus-width = <4>;
|
|
disable-wp;
|
|
cap-mmc-highspeed;
|
|
cap-sd-highspeed;
|
|
card-detect-delay = <200>;
|
|
mmc-ddr-1_8v;
|
|
mmc-hs200-1_8v;
|
|
sd-uhs-sdr12;
|
|
sd-uhs-sdr25;
|
|
sd-uhs-sdr50;
|
|
sd-uhs-sdr104;
|
|
};
|
|
|
|
&i2c1 {
|
|
status = "okay";
|
|
clock-frequency = <100000>;
|
|
|
|
pac193x: pac193x@10 {
|
|
compatible = "microchip,pac1934";
|
|
reg = <0x10>;
|
|
samp-rate = <64>;
|
|
status = "okay";
|
|
ch1: channel0 {
|
|
uohms-shunt-res = <10000>;
|
|
rail-name = "VDDREG";
|
|
channel_enabled;
|
|
};
|
|
ch2: channel1 {
|
|
uohms-shunt-res = <10000>;
|
|
rail-name = "VDDA25";
|
|
channel_enabled;
|
|
};
|
|
ch3: channel2 {
|
|
uohms-shunt-res = <10000>;
|
|
rail-name = "VDD25";
|
|
channel_enabled;
|
|
};
|
|
ch4: channel3 {
|
|
uohms-shunt-res = <10000>;
|
|
rail-name = "VDDA_REG";
|
|
channel_enabled;
|
|
};
|
|
};
|
|
};
|
|
|
|
&mac1 {
|
|
status = "okay";
|
|
phy-mode = "sgmii";
|
|
phy-handle = <&phy1>;
|
|
phy1: ethernet-phy@9 {
|
|
reg = <9>;
|
|
ti,fifo-depth = <0x1>;
|
|
};
|
|
};
|
|
|
|
&qspi {
|
|
status = "okay";
|
|
num-cs = <1>;
|
|
|
|
flash0: flash@0 {
|
|
compatible = "spi-nand";
|
|
reg = <0x0>;
|
|
spi-tx-bus-width = <4>;
|
|
spi-rx-bus-width = <4>;
|
|
spi-max-frequency = <20000000>;
|
|
spi-cpol;
|
|
spi-cpha;
|
|
};
|
|
};
|